Abstract: Systems, methods, and circuits provide a time to digital converter comprising a sigma-delta modulator. The sigma-delta based time to digital converter may receive an analog signal representing a phase error between a reference clock signal and a feedback clock signal and generate a digital signal representing the phase error. The sigma-delta modulator may comprise a subtractor, an integrator, a feedback path, and a quantizer. The subtractor may receive the analog signal and subtract a feedback signal from the analog signal and the integrator may integrate the output of the subtractor. The sigma-delta modulator may accumulate a voltage or a charge over a capacitor as pulses are received from the analog signal and after a number of clock cycles, the capacitor may be discharged to generate a pulse in an output signal.

Abstract: Systems, methods, and circuits provide a digital frequency synthesizer where the output of the frequency synthesizer is a fractional factor of an input signal frequency. The digital frequency synthesizer may comprise a time to digital converter. A ramp offset signal may be added to the output of the time to digital converter. The ramp offset signal may be added to the output of a TDC until a reference dock signal reaches a value of pi. At such a point, the reference clock signal may be switched and the ramp offset signal may be restarted. As such, a frequency offset may be introduced at the input of the time to digital converter where the frequency offset may be modified by changing the slope of the ramp offset signal.

Abstract: Systems, methods, and circuits provide a time to digital converter comprising a sigma-delta modulator. The sigma-delta based time to digital converter may receive an analog signal representing a phase error between a reference clock signal and a feedback clock signal and generate a digital signal representing the phase error. The sigma-delta modulator may comprise a subtractor, an integrator, a feedback path, and a quantizer. The subtractor may receive the analog signal and subtract a feedback signal from the analog signal and the integrator may integrate the output of the subtractor. The sigma-delta modulator may accumulate a voltage or a charge over a capacitor as pulses are received from the analog signal and after a number of clock cycles, the capacitor may be discharged to generate a pulse in an output signal.

Abstract: Systems, methods, and circuits provide a digital frequency synthesizer where the output of the frequency synthesizer is a fractional factor of an input signal frequency. The digital frequency synthesizer may comprise a time to digital converter. A ramp offset signal may be added to the output of the time to digital converter. The ramp offset signal may be added to the output of a TDC until a reference dock signal reaches a value of pi. At such a point, the reference clock signal may be switched and the ramp offset signal may be restarted. As such, a frequency offset may be introduced at the input of the time to digital converter where the frequency offset may be modified by changing the slope of the ramp offset signal.