Patents by Inventor Pardeep Juneja

Pardeep Juneja has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10296703
    Abstract: The present disclosure relates to a system and method for visualization of fixing of design rule violations in an electronic circuit design. Embodiments may include displaying at a graphical user interface at least a portion of an electronic design having at least one shape associated therewith and identifying one or more electronic design rules associated with the at least one shape. In response to identifying, embodiments may include determining a proposed shape based upon, at least in part, the one or more electronic design rules associated with the at least one shape, wherein the proposed shape is at least one of a trim shape, a bridge shape, and a patch shape and displaying the proposed shape at the graphical user interface.
    Type: Grant
    Filed: September 20, 2017
    Date of Patent: May 21, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: Pardeep Juneja, Jean-Marc Bourguet, Joyjeet Bose, Sachin Shrivastava, Yashu Gupta, Ankur Chaplot
  • Patent number: 9064063
    Abstract: Disclosed encompasses method, system, computer program product for implementing interactive checking of constraints. Various embodiments bridge schematic design environment and layout environment with a binder mapping process and utilize connectivity information from the schematic design to identify constraint violations early in the physical design stage. The method identifies or creates a layout and identifies or generates an object for a modification process. The method may take snapshot(s) of the design database or may use one or more logs for restoring the design database. The method then identifies or creates scratch pad(s) and performs modification process on the object to generate a change. The method uses scratch pad(s) and trigger(s) to perform constraint checking during the modification process to provide interactive feedback in response to the modification process before committing the change to the persistent database.
    Type: Grant
    Filed: April 12, 2012
    Date of Patent: June 23, 2015
    Assignee: Cadence Design Systems, Inc.
    Inventors: Henry Yu, Joshua Baudhuin, Regis Colwell, Harsh Deshmane, Elias L. Fallon, Sanjib Ghosh, Anjna Khanna, Yinnie Lee, Harindranath Parameswaran, Pardeep Juneja, Roland Ruehl, Simon Simonian, Hui Xu, Timothy Rosek
  • Patent number: 8839183
    Abstract: A computer-implemented method, system and computer program product for visualizing derived layer shapes of an integrated circuit design are disclosed. The computer-implemented method, system and computer program product include visualizing the derived layer shapes on a layout canvas; providing a step by step process for visualizing each derived layer shape as each derived layer shape is generated; and providing a hierarchy of intermediate derived layers based upon the step by step process.
    Type: Grant
    Filed: January 31, 2013
    Date of Patent: September 16, 2014
    Assignee: Cadence Design Systems, Inc.
    Inventors: Pardeep Juneja, Sanjiib Ghosh, Harindranath Parameswaran
  • Publication number: 20140215422
    Abstract: A computer-implemented method, system and computer program product for visualizing derived layer shapes of an integrated circuit design are disclosed. The computer-implemented method, system and computer program product include visualizing the derived layer shapes on a layout canvas; providing a step by step process for visualizing each derived layer shape as each derived layer shape is generated; and providing a hierarchy of intermediate derived layers based upon the step by step process.
    Type: Application
    Filed: January 31, 2013
    Publication date: July 31, 2014
    Applicant: Cadence Design Systems, Inc.
    Inventors: Pardeep JUNEJA, Sanjiib GHOSH, Harindranath PARAMESWARAN
  • Patent number: 8694943
    Abstract: Disclosed are methods and systems for implementing constraint and connectivity aware physical designs. The method or system provides a connectivity-aware environment to implement electronic designs. For example, the method interactively determines whether an electronic design complies with various constraints by using connectivity information in a nearly real-time manner while the electronic design is being created in some embodiments. The method or system uses the connectivity information provided by a connectivity engine or specified by designers to present feedback to a user as to whether a newly created object or a newly modified object complies or violates certain relevant constraints in an interactive manner or in nearly real-time without having to perform such constraints checking in batch mode. The method further enables one to implement electronic designs by using connectivity information without performing extraction on layouts or rebuilding nets.
    Type: Grant
    Filed: April 12, 2012
    Date of Patent: April 8, 2014
    Assignee: Cadence Design Systems, Inc.
    Inventors: Henry Yu, Roland Ruehl, Elias L. Fallon, Regis Colwell, Joshua Baudhuin, Hui Xu, Harsh Deshmane, Yinnie Lee, Simon Simonian, Harindranath Parameswaran, Pardeep Juneja, Anjna Khanna, Sanjib Ghosh, Timothy Rosek
  • Patent number: 8555237
    Abstract: An apparatus and method for reporting design rule violations of an integrated circuit design includes collecting data from a design rule checker module, processing the data, and displaying design rule violations onto the layout. The display of the design rule violations may be interactive by including hypertext links to specifications, text bubbles with violation explanations, measurements, highlighting areas of the layout corresponding to a particular rule, and providing hierarchically expandable nodes for constraint violations in a browser.
    Type: Grant
    Filed: July 5, 2012
    Date of Patent: October 8, 2013
    Assignee: Cadence Design Systems, Inc.
    Inventors: Pardeep Juneja, Om Kanwar, Harindranath Parameswaran