Abstract: Configuration data indicative of interface requirements for interfacing to a host adapter card are automatically serially loaded on reset from an external device on the card into a host adapter integrated circuit on the card. A driver program can then read the configuration data from the host adapter integrated circuit and thereby determine how to interface with the host adapter card.

Abstract: Configuration data indicative of interface requirements for interfacing to a host adapter card are automatically serially loaded on reset from an external device on the card into host adapter integrated circuit on the card. A driver program can then read the configuration data from the host adapter integrated circuit and thereby determine how to interface with the host adapter card.

Abstract: The host adapter integrated circuit is a one chip high performance bus master host adapter for (i) connecting a first bus having a specified protocol for transferring information over the first bus and a first data transfer speed to a second bus having a specified protocol for transferring information over the second bus and a second data transfer speed, and (ii) transferring information between the two buses. The host adapter integrated circuit, hereinafter host adapter, includes a novel reduced instruction set computing (RISC) processor, a first interface module circuit connectable to the first bus and coupled to the RISC processor, a second interface module circuit connectable to the second bus and coupled to the RISC processor, and a memory circuit means connected to the first interface module circuit and to the second interface module circuit and coupled to the RISC processor.