Abstract: The present invention relates to a digital fractional-N phase lock loop (PLL) (1), comprising: —a forward path comprising a phase detector (4), a digital loop filter (3), a digitally-controlled oscillator (2); —a feedback path comprising a feedback element (5, 6), wherein a phase detector output of the phase detector (4) is connected to a loop filter input of the digital loop filter (3) for providing an unfiltered control signal (Suf), and a loop filter output of the digital loop filter (3) is connected to an oscillator input of the digitally-controlled oscillator (2) for providing a filtered control signal (Sf), wherein the unfiltered control signal (Su) and the filtered control signal (Sf) each contain a periodic error signal having a mutually different amplitude; —a digital-to-time converter (7), arranged in the forward or the feedback path and connected with a converter output to a phase detector input of the phase detector (4); —a spur compensation unit (10) arranged with two inputs and an output, wherei

Abstract: A receiver for a Pulsed Eddy Current (PEC) system configured to detect a changing electromagnetic field generated by eddy currents induced in an object of an electrically conductive material. The receiver includes an electrically conductive receiver coil, a high-voltage receiver channel, a low-voltage receiver channel, and an over-voltage protection connected between the receiver coil and the LVRC. The OVP includes a bias circuit B, a diode D connected between the receiver coil and the bias circuit, and a capacitor C connected between the bias circuit and the LVRC.

Abstract: A receiver for a Pulsed Eddy Current (PEC) system configured to detect a changing electromagnetic field generated by eddy currents induced in an object of an electrically conductive material. The receiver includes an electrically conductive receiver coil, a high-voltage receiver channel, a low-voltage receiver channel, and an over-voltage protection connected between the receiver coil and the LVRC. The OVP includes a bias circuit B, a diode D connected between the receiver coil and the bias circuit, and a capacitor C connected between the bias circuit and the LVRC.