Abstract: A distributed system implementation for cache coherence comprises distinct agent interface units, coherency controllers, and memory interface units. The agents send requests in the form of read and write transactions. The system also includes a memory that includes coherent memory regions. The memory is in communication with the agents. The system includes a coherent interconnect in communication with the memory and the agents. The system includes a second identical coherent interconnect in communication with the memory and the agents.

Abstract: A system, and corresponding method, is described for updating or calculating ECC where the transaction volume is significantly reduced from a read-modify-write to a write, which is more efficient and reduces demand on the data access bandwidth. The invention can be implemented in any chip, system, method, or HDL code that perform protection schemes and require ECC calculation, of any kind. Embodiments of the invention enable IPs that use different protections schemes to reduce power consumption and reduce bandwidth access to more efficiently communicate or exchange information.

Abstract: A system and method are disclosed with the ability to track usage of information, which patterns, and determine the most frequently used patterns to be stored and updated in a directory, thereby controlling and reducing the size allocated to storing information in the directory. The size is reduced by limiting address bits thereby allowing subsystems to avoid transmitting, storing, and operating upon excessive address information.

Abstract: A system and method are disclosed with the ability to track usage of information and determine commonly used patterns to be stored and updated in a directory. The information includes counter values that represent the frequency of occurrence of a pattern that is committed to the directory. Thus, allows the system to control and reduce the size allocated to storing information in the directory because the size is reduced by limiting address bits. This, in turn, creates additional benefits in speed and power because it allows subsystems to avoid transmitting, storing, and operating upon excessive address information.