Patents by Inventor Parinda Mekara

Parinda Mekara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Non-linear current IDAC with synthesis in time domain
    Patent number: 9307590
    Abstract: An electrical current (“I”) digital-to-analog converter (“IDAC”) (60) supplies a specified electrical current to at least one light emitting diode. The IDAC (60) includes a plurality of current sources/sinks (26): a. that are connected in parallel so a total amount of current flowing through the at least one LED equals the sum of their individual electrical currents; and b. at any instant in time individual current sources/sinks (26) are either: 1. turned on: or 2. turned off. When the specified electrical current being supplied exceeds a pre-established threshold (94), a sequence of individual current sources/sinks (26) are turned on ever more quickly to produce a. non-linearly increasing electrical current.
    Type: Grant
    Filed: August 28, 2014
    Date of Patent: April 5, 2016
    Assignee: Dialog Semiconductor (UK) Limited
    Inventors: Sorin Laurentiu Negru, Sule Cetin, Parinda Mekara
  • Non-Linear Current IDAC With Synthesis In Time Domain
    Publication number: 20160066371
    Abstract: An electrical current (“I”) digital-to-analog converter (“IDAC”) (60) supplies a specified electrical current to at least one light emitting diode. The IDAC (60) a plurality of current sources/sinks (26): a. that are connected in parallel so a total amount of current flowing through the at least one LED equals the sum of their individual electrical currents; and b. at any instant in time individual current sources/sinks (26) are either: 1. turned on: or 2. turned off. When the specified electrical current being supplied exceeds a pre-established threshold (94), a sequence of individual current sources/sinks (26) are turned on ever more quickly to produce a non-linearly increasing electrical current.
    Type: Application
    Filed: August 28, 2014
    Publication date: March 3, 2016
    Inventors: Sorin Laurentiu Negru, Sule Cetin, Parinda Mekara
  • High speed FIFO synchronous programmable full and empty flag generation
    Patent number: 7116599
    Abstract: An apparatus comprising a flag generation circuit configured to generate a full flag signal in response to (i) a read clock signal, (ii) a write clock signal and (iii) a look ahead bitwise comparison configured to detect when a read count signal and a write count signal are equal.
    Type: Grant
    Filed: September 20, 2001
    Date of Patent: October 3, 2006
    Assignee: Cypress Semiconductor Corp.
    Inventors: Johnie Au, Chia Jen Chang, Parinda Mekara
  • High speed asynchronous and programmable state machine for generating almost full synchronous flags in a synchronous FIFO
    Patent number: 6970392
    Abstract: A state machine comprising a first input receiving a first read clock, a second input receiving a first write clock, a third input receiving a first programmable Almost Full look-ahead signal, a fourth input receiving a second read clock, a fifth input receiving a second write clock, and a sixth input receiving a second programmable Almost Full look-ahead signal is disclosed. The state machine manipulates the inputs to produce an output signal representing an Almost Full output flag that is at a first logic state when a FIFO is Almost Full and is at a second logic state when the FIFO is Not Almost Full.
    Type: Grant
    Filed: June 29, 2001
    Date of Patent: November 29, 2005
    Assignee: Cypress Semiconductor Corp.
    Inventors: Johnie Au, Chia Jen Chang, Parinda Mekara
  • High speed FIFO synchronous programmable full and empty flag generation
    Patent number: 6525980
    Abstract: An apparatus comprising a flag generation circuit configured to generate an empty flag signal in response to (i) a read clock, (ii) a write clock and (iii) a look ahead bitwise comparison configured to detect when a write count signal minus a read count signal is equal to 1.
    Type: Grant
    Filed: September 20, 2001
    Date of Patent: February 25, 2003
    Assignee: Cypress Semiconductor Corp.
    Inventors: Johnie Au, Chia Jen Chang, Parinda Mekara
  • High speed asynchronous and programmable state machine for generating almost empty synchronous flags in a synchronous FIFO
    Patent number: 6445635
    Abstract: A state machine comprising a first input receiving a first write clock, a second input receiving a first read clock, a third input receiving a first programmable Almost Empty look-ahead signal, a fourth input receiving a second write clock, a fifth input receiving a second read clock, and a sixth input receiving a second programmable Almost Empty look-ahead signal is disclosed. The state machine manipulates the inputs to produce an output signal representing an Almost Empty output flag that is at a first logic state when a FIFO is Almost Empty and is at a second logic state when the FIFO is Not Almost Empty.
    Type: Grant
    Filed: June 30, 2001
    Date of Patent: September 3, 2002
    Assignee: Cypress Semiconductor Corporation
    Inventors: Johnie Au, Chia Jen Chang, Parinda Mekara