Patents by Inventor Parissa Najdesamii
Parissa Najdesamii has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240038760Abstract: An integrated circuit (IC), including a first row of cells including a first set of one or more complementary metal oxide semiconductor (CMOS) signal processing cells including a first diffusion region; a second row of cells including a second set of one or more CMOS signal processing cells including a second diffusion region; and a first body tie electrically coupling a first voltage rail to the first and second diffusion regions.Type: ApplicationFiled: August 1, 2022Publication date: February 1, 2024Inventors: Manjanaika CHANDRANAIKA, Parissa NAJDESAMII, Kamesh MEDISETTI, Iranagouda Shivanagouda NAGANAGOUDRA
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Patent number: 10109619Abstract: In an aspect of the disclosure, a MOS device for reducing routing congestion caused by using split n-well cells in a merged n-well circuit block is provided. The MOS device may include a first set of cells adjacent to each other in a first direction. The MOS device may include a second set of cells adjacent to each other in the first direction and adjacent to the first set of cells in a second direction. The second set of cells each may include a first n-well, a second n-well, and a third n-well separated from each other. The MOS device may include an interconnect extending in the first direction in the second set of cells. The interconnect may provide a voltage source to the first n-well of each of the second set of cells.Type: GrantFiled: June 6, 2016Date of Patent: October 23, 2018Assignee: QUALCOMM IncorporatedInventors: Harshat Pant, Mohammed Yousuff Shariff, Parissa Najdesamii, Ramaprasath Vilangudipitchai, Divjyot Bhan
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Publication number: 20170352649Abstract: In an aspect of the disclosure, a MOS device for reducing routing congestion caused by using split n-well cells in a merged n-well circuit block is provided. The MOS device may include a first set of cells adjacent to each other in a first direction. The MOS device may include a second set of cells adjacent to each other in the first direction and adjacent to the first set of cells in a second direction. The second set of cells each may include a first n-well, a second n-well, and a third n-well separated from each other. The MOS device may include an interconnect extending in the first direction in the second set of cells. The interconnect may provide a voltage source to the first n-well of each of the second set of cells.Type: ApplicationFiled: June 6, 2016Publication date: December 7, 2017Inventors: Harshat PANT, Mohammed Yousuff SHARIFF, Parissa NAJDESAMII, Ramaprasath VILANGUDIPITCHAI, Divjyot BHAN
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Patent number: 9483600Abstract: A MOS device includes a number of standard cells configured to reduce routing congestions while providing area savings on the MOS device. The standard cells may be single height standard cells that share an n-type well isolated from other nearby n-type wells. The input and output signal pins of the single height standard cells may be configured in a lowest possible metal layer (e.g., M1), while the secondary power pins of the single height standard cells may be configured in a higher metal layer (e.g., M2). Interconnects supplying power to secondary power pins may be configured along vertical tracks and shared among different sets of standard cells, which may reduce the number of vertical tracks used in the MOS device. The number of available horizontal routing tracks in the MOS device may remain unaffected, since the horizontal tracks already used by the primary power/ground mesh are used for power connection.Type: GrantFiled: March 11, 2015Date of Patent: November 1, 2016Assignee: QUALCOMM INCORPORATEDInventors: Mamta Bansal, Uday Doddannagari, Paras Gupta, Ramaprasath Vilangudipitchai, Parissa Najdesamii, Dorav Kumar, Nitin Partani
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Patent number: 9473113Abstract: An integrated circuit (IC) is disclosed herein for managing power with flip-flops having a retention feature. In an example aspect, an IC includes a constant power rail, a collapsible power rail, multiple flip-flops, and power management circuitry. Each flip-flop of the multiple flip-flops includes a master portion that is coupled to the collapsible power rail and a slave portion that is coupled to the constant power rail. The power management circuitry is configured to combine a clock signal and a retention signal into a combined control signal and to provide the combined control signal to each flip-flop of the multiple flip-flops.Type: GrantFiled: September 24, 2015Date of Patent: October 18, 2016Assignee: QUALCOMM IncorporatedInventors: Harshat Pant, Ramaprasath Vilangudipitchai, Divjyot Bhan, Lipeng Cao, Sai Pradeep Kochuri, Parissa Najdesamii
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Patent number: 9190358Abstract: A semiconductor apparatus is provided herein for buffering of nets routed through one or more areas associated with a first power domain that is different from a second power domain associated with the buffers and the buffered nets by limiting placement of these buffers in patterned areas associated with the second power domain. This provides for the routing of the buffered nets to be determined not only based on the shortest distance to travel from Point A to Point B, but also takes into account routing congestion on the semiconductor apparatus. Consequently, if an area on the semiconductor apparatus is congested, the buffered nets may be routed around the congestion. As such, although a path taken by a particular signal through the integrated circuit is not a direct route, it may still be of a distance to support a speed at which the particular signal needs to be transferred.Type: GrantFiled: September 12, 2014Date of Patent: November 17, 2015Assignee: QUALCOMM IncorporatedInventors: Sundararajan Ranganathan, Paras Gupta, Raghavendra Dasegowda, Rajesh Verma, Parissa Najdesamii
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Publication number: 20150262936Abstract: A MOS device includes a number of standard cells configured to reduce routing congestions while providing area savings on the MOS device. The standard cells may be single height standard cells that share an n-type well isolated from other nearby n-type wells. The input and output signal pins of the single height standard cells may be configured in a lowest possible metal layer (e.g., M1), while the secondary power pins of the single height standard cells may be configured in a higher metal layer (e.g., M2). Interconnects supplying power to secondary power pins may be configured along vertical tracks and shared among different sets of standard cells, which may reduce the number of vertical tracks used in the MOS device. The number of available horizontal routing tracks in the MOS device may remain unaffected, since the horizontal tracks already used by the primary power/ground mesh are used for power connection.Type: ApplicationFiled: March 11, 2015Publication date: September 17, 2015Inventors: Mamta BANSAL, Uday DODDANNAGARI, Paras GUPTA, Ramaprasath VILANGUDIPITCHAI, Parissa NAJDESAMII, Dorav KUMAR, Nitin PARTANI
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Publication number: 20150200667Abstract: Provided are systems and methods for reducing power consumption in the interface and routing circuitry associated with various core modules of an integrated circuit or system. One system includes core modules, glue logic domains adapted to interface the plurality of core modules, and a power controller electrically coupled to the glue logic domains. Each glue logic domain includes a glue logic module implemented as a soft macro with metal traces extending beyond an extent of the glue logic module. The power controller decouples power from selected glue logic domains based on control signals and/or detected power down states of core modules and/or other glue logic domains. The power controller facilitates the power transitions using logic state retention, logic state clamping, ordered or scheduled transitioning, and/or other power transition systems and methods.Type: ApplicationFiled: January 15, 2014Publication date: July 16, 2015Applicant: QUALCOMM IncorporatedInventors: Shiva Ram Chandrasekaran, Chandrasekhar Reddy Singasani, Joey Dacanay, Mamta Bansal, Arman Ohanian, Satish Raj, Kiran Srinivasa Sastry, Abhirami Senthilkumaran, Tarek Zghal, Parissa Najdesamii, Sunil Kumar
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Publication number: 20140374873Abstract: A semiconductor apparatus is provided herein for buffering of nets routed through one or more areas associated with a first power domain that is different from a second power domain associated with the buffers and the buffered nets by limiting placement of these buffers in patterned areas associated with the second power domain. This provides for the routing of the buffered nets to be determined not only based on the shortest distance to travel from Point A to Point B, but also takes into account routing congestion on the semiconductor apparatus. Consequently, if an area on the semiconductor apparatus is congested, the buffered nets may be routed around the congestion. As such, although a path taken by a particular signal through the integrated circuit is not a direct route, it may still be of a distance to support a speed at which the particular signal needs to be transferred.Type: ApplicationFiled: September 12, 2014Publication date: December 25, 2014Inventors: Sundararajan Ranganathan, Paras Gupta, Raghavendra Dasegowda, Rajesh Verma, Parissa Najdesamii
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Patent number: 8853815Abstract: A semiconductor apparatus is provided herein for buffering of nets routed through one or more areas associated with a first power domain that is different from a second power domain associated with the buffers and the buffered nets by limiting placement of these buffers in patterned areas associated with the second power domain. This provides for the routing of the buffered nets to be determined not only based on the shortest distance to travel from Point A to Point B, but also takes into account routing congestion on the semiconductor apparatus. Consequently, if an area on the semiconductor apparatus is congested, the buffered nets may be routed around the congestion. As such, although a path taken by a particular signal through the integrated circuit is not a direct route, it may still be of a distance to support a speed at which the particular signal needs to be transferred.Type: GrantFiled: March 14, 2013Date of Patent: October 7, 2014Assignee: QUALCOMM IncorporatedInventors: Sundararajan Ranganathan, Paras Gupta, Raghavendra Dasegowda, Rajesh Verma, Parissa Najdesamii
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Publication number: 20140264715Abstract: A semiconductor apparatus is provided herein for buffering of nets routed through one or more areas associated with a first power domain that is different from a second power domain associated with the buffers and the buffered nets by limiting placement of these buffers in patterned areas associated with the second power domain. This provides for the routing of the buffered nets to be determined not only based on the shortest distance to travel from Point A to Point B, but also takes into account routing congestion on the semiconductor apparatus. Consequently, if an area on the semiconductor apparatus is congested, the buffered nets may be routed around the congestion. As such, although a path taken by a particular signal through the integrated circuit is not a direct route, it may still be of a distance to support a speed at which the particular signal needs to be transferred.Type: ApplicationFiled: March 14, 2013Publication date: September 18, 2014Applicant: QUALCOMM IncorporatedInventors: Sundararajan Ranganathan, Paras Gupta, Raghavendra Dasegowda, Rajesh Verma, Parissa Najdesamii
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Patent number: 7948292Abstract: An integrated circuit includes first and second voltage domains. The first voltage domain is associated with a positive voltage supply grid and the second voltage domain is associated with a selectably on voltage supply grid. A switch is used to selectably switch on and off the selectably on voltage supply grid to power the second voltage domain. A buffer cell cluster of at least on initial buffer cell and a pair of insulator cells is coupled to the positive voltage supply grid electrically independent of the nodes of a switch and is capable of buffering a feed-through signal having a logic one voltage level defined substantially at the voltage level of the positive voltage supply grid. The buffer cell cluster has two distal ends. buffer cell cluster, at one distal end, is coupled to a first insulator cell of the pair of cells while, at the other distal end, the buffer cell cluster is coupled to a second insulator cell of the pair of the cells.Type: GrantFiled: June 5, 2008Date of Patent: May 24, 2011Assignee: ATI Technologies ULCInventors: Robert Chiu, Denitza Tchoevska, Parissa Najdesamii, Mark H. Sternberg