Abstract: A high input impedance switched capacitor amplifier is disclosed. The switched capacitor amplifier includes at least a first buffer circuit configured to charge a first plurality of capacitors during a first time period. A switch circuit is configured to, during a second time period, cause a modification of an amount of charge stored on one of the first plurality of capacitors by coupling an input signal directly to the one of first plurality of capacitors. An amplifier circuit is configured to, based on a sampling voltage present on one of the first plurality of capacitors, generate an output signal.

Abstract: Comparators are implemented in many circuits, including analog-to-digital converters (ADCs). Some ADCs demand high bandwidth, low power consumption, and high speed. To address these requirements, a comparator circuit can be implemented without a separate pre-amplifier, where a sampling network drives a latch directly. Specifically, the comparator circuit integrates a pre-amplifier within the latch in a manner that ensures low power and high speed operation.

Abstract: Comparators are implemented in many circuits, including analog-to-digital converters (ADCs). Some ADCs demand high bandwidth, low power consumption, and high speed. To address these requirements, a comparator circuit can be implemented without a separate pre-amplifier, where a sampling network drives a latch directly. Specifically, the comparator circuit integrates a pre-amplifier within the latch in a manner that ensures low power and high speed operation.

Abstract: A pipeline analog-to-digital converter (ADC) converts an analog input signal over several stages, where a stage generates a residue for the subsequent stage to digitize. The residue is generated by coarsely quantizing the analog input signal to generate a digital code, which is used to reconstruct the analog input signal, and the residue is the difference between the analog input signal and the reconstructed version of the analog input signal. The coarse quantization can have errors which are attributed to comparator offsets and bandwidth mismatch. To estimate the comparator offsets while being insensitive to bandwidth mismatch, peak and trough detectors are used to track maximum and minimum values of the residue or the output of the ADC over time, and an expected value estimating the comparator offset can be computed based on the maximum and minimum values. The expected value advantageously “averages” out the bandwidth mismatch contribution to the offset.

Abstract: A pipeline analog-to-digital converter (ADC) converts an analog input signal over several stages, where a stage generates a residue for the subsequent stage to digitize. The residue is generated by coarsely quantizing the analog input signal to generate a digital code, which is used to reconstruct the analog input signal, and the residue is the difference between the analog input signal and the reconstructed version of the analog input signal. The coarse quantization can have errors which are attributed to comparator offsets and bandwidth mismatch. To estimate the comparator offsets while being insensitive to bandwidth mismatch, peak and trough detectors are used to track maximum and minimum values of the residue or the output of the ADC over time, and an expected value estimating the comparator offset can be computed based on the maximum and minimum values. The expected value advantageously “averages” out the bandwidth mismatch contribution to the offset.

Abstract: Embodiments of the present invention may provide an improved apparatus and method for reducing distortion in analog circuits. A circuit in accordance with the present invention may include a main path comprising an analog circuit with an input impedance, a source impedance representing the impedance of an input network driving the analog circuit, and a cancellation path. The cancellation path may be in parallel to the main path and may generate a cancelling non-linear current to substantially cancel a non-linear current drawn to the input impedance, resulting in a decrease of non-liner current flowing through the source impedance.

Abstract: Embodiments of the present invention may provide an improved apparatus and method for reducing distortion in analog circuits. A circuit in accordance with the present invention may include a main path comprising an analog circuit with an input impedance, a source impedance representing the impedance of an input network driving the analog circuit, and a cancellation path. The cancellation path may be in parallel to the main path and may generate a cancelling non-linear current to substantially cancel a non-linear current drawn to the input impedance, resulting in a decrease of non-liner current flowing through the source impedance.

Abstract: A method and device involve a circuit having a switched capacitor network that is switchably connected to an input signal. A randomly determined amount of dither is injected into a circuit having a switched capacitor network that is switchably connected to an input signal. After injecting the dither, at least one correlation value is determined. The correlation value(s) indicates a degree of correlation between the injected dither and an output of the circuit. Distortion caused by an amount of charge kicked back into the circuit when the switched capacitor network is reconnected to the input signal may then be reduced. The reduction is calculated as a function of the correlation value(s).

Abstract: A method and device involve a circuit having a switched capacitor network that is switchably connected to an input signal. A randomly determined amount of dither is injected into a circuit having a switched capacitor network that is switchably connected to an input signal. After injecting the dither, at least one correlation value is determined. The correlation value(s) indicates a degree of correlation between the injected dither and an output of the circuit. Distortion caused by an amount of charge kicked back into the circuit when the switched capacitor network is reconnected to the input signal may then be reduced. The reduction is calculated as a function of the correlation value(s).

Abstract: A process allows for the modification of the least-means-square (LMS) algorithm to remove perturbations associated with measured signals in an analog-to-digital converter (ADC). The process includes measuring the perturbations and determining a coefficient associated with the perturbations. The LMS algorithm is modified in accordance with whether a digital or an analog correction of the inter-stage error of a residue amplifier on the ADC is to be made.

Abstract: An integrated circuit allows for the isolation of the input of an analog-to-digital converter (ADC) from a summing-node (SNS) algorithm. The integrated circuit contains a gating device that is controlled by bits of a flash analog-to-digital converter (ADC) to gate input samples to sub-ranges that are used by the SNS algorithm. A single sub-range is chosen to be used by the SNS algorithm.

Abstract: A process allows for the modification of the least-means-square (LMS) algorithm to remove perturbations associated with measured signals in an analog-to-digital converter (ADC). The process includes measuring the perturbations and determining a coefficient associated with the perturbations. The LMS algorithm is modified in accordance with whether a digital or an analog correction of the inter-stage error of a residue amplifier on the ADC is to be made.

Abstract: An integrated circuit allows for the isolation of the input of an analog-to-digital converter (ADC) from a summing-node (SNS) algorithm. The integrated circuit contains a gating device that is controlled by bits of a flash analog-to-digital converter (ADC) to gate input samples to sub-ranges that are used by the SNS algorithm. A single sub-range is chosen to be used by the SNS algorithm.