Abstract: A system and method uses a set of processors that each perform a logic function to identify portions of a data source meeting a criteria. Each logic function is performed against a row of a column of the data source, and a value that is derived from the criteria for that logic function, which is also derived from the criteria. The output of each of the logic functions is applied as an address to a table that has been configured to read true at the addresses corresponding to the criteria being met, and false otherwise. Data from the row of the database table having a table value of true are retrieved from the data source.

Abstract: A system and method processes join requests via independently running engines. A build side table to be joined is allocated among high speed memories of the engines. Each row of a probe side are allocated to the engine likely to have build side data corresponding to the row, and the engine then performs the join. Aggregation statistics may be computed by distributing the information across the engines.

Abstract: A computer readable medium includes executable instructions to describe an intellectual property core with a key check mechanism configured to compare an external key with an internal key in response to a specified event. A pending instruction is executed in response to a match between the external key and the internal key. An unexpected act is performed in response to a mismatch between the external key and the internal key.

Abstract: A method and system for adaptive multi-protocol resilient packet ring (RPR) processing are provided. The present invention provides optimal handling operations targeted for both legacy and evolving RPR functions related to topology discovery, fairness algorithms, and control-packet manipulation. Further, the present invention utilizes out-band paths, unique data and instruction memory constructs, and pipeline and multi-thread features to provide wire-rate performance. In one embodiment, a system of the present invention includes instruction memory; a fetch unit associated with instruction memory; a decode unit associated with the fetch unit; at least one execution unit associated with the decode unit; a load/store unit associated with the at least one execution unit; and data memory associated with the load/store unit.

Abstract: The present invention addresses the need for improved network data handling with a flexible, single point solution for packet header processing of data packets in a variable format transfer environment without associated performance or rate degradation. The present invention introduces a programmable or reconfigurable data packet header processor, wherein various registers (50, 55 and 60) of a chip are selectively programmed with a set of values that map the length (48) and location (44) of various header fields (20, 23, 25) to their position measured from the start of the packet (29). Unlike dedicated hardware solutions, these updateable registers are designed to store length (48), position (44) and type (40) data relating to multiple packet formats to improve extraction of packet header information by guiding the extraction to the exact point of the desired field information.