Patents by Inventor Paritosh Rajora

Paritosh Rajora has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • METHOD TO PROTECT MAGNETIC BITS DURING PLANARIZATION
    Publication number: 20130001188
    Abstract: The embodiments disclose a method to protect magnetic bits during carbon field planarization, including depositing a stop layer upon magnetic bits and magnetic film of a patterned stack, depositing a carbon fill layer on the stop layer and using the stop layer during planarization and etch-back of the carbon field to protect the patterned stack magnetic bits during the carbon field planarization.
    Type: Application
    Filed: June 30, 2011
    Publication date: January 3, 2013
    Applicant: SEAGATE TECHNOLOGY, LLC
    Inventors: David Kuo, Michael R. Feldbaum, Paritosh Rajora, Hieu Lam
  • PATTERNING MAGNETIC RECORDING MEDIA WITH ION IMPLANTATION UTILIZING A COMBINATION OF HEAVY AND LIGHT ION SPECIES
    Publication number: 20100300874
    Abstract: A patterned magnetic layer is formed by bombardment of a masked high Mrt magnetic layer with a combination of both heavy ion species and light ion species. The method can be implemented as sequential process steps or in a single process step with the proper heavy/light ion species mixture. Advantageously, the combined heavy/light ion species bombardment method results in a patterned magnetic layer having high topographical uniformity across its surface.
    Type: Application
    Filed: May 28, 2009
    Publication date: December 2, 2010
    Inventors: David Shiao-Min Kuo, Dieter Weller, Jan-Ulrich Thiele, Justin Hwu, Paritosh Rajora
  • Method for minimizing the critical dimension growth of a feature on a semiconductor wafer
    Patent number: 6774046
    Abstract: A method for minimizing the critical dimension growth of a feature on a semiconductor wafer includes performing an etch operation in a reactor 20 and controlling the temperature of the wafer 26 by controlling the pressure of the gas contacting the backside of the wafer 26 and/or providing a heat source 56 such as for example in the chuck 46 or electrode 28 associated with the wafer 26 in order to heat the wafer 26.
    Type: Grant
    Filed: June 13, 2001
    Date of Patent: August 10, 2004
    Assignee: Tegal Corporation
    Inventors: Stephen P. DeOrnellas, Alferd Cofer, Leslie G. Jerde, Kurt A. Olson, Paritosh Rajora
  • Method and apparatus for etching a semiconductor wafer with features having vertical sidewalls
    Patent number: 6492280
    Abstract: A method and apparatus provide for etching a semiconductor wafer using a two step physical etching and a chemical etching process in order to create vertical sidewalls required for high density DRAMs and FRAMs.
    Type: Grant
    Filed: March 2, 2000
    Date of Patent: December 10, 2002
    Assignee: Tegal Corporation
    Inventors: Stephen P. DeOrnellas, Alferd Cofer, Paritosh Rajora
  • Method for minimizing the critical dimension growth of a feature on a semiconductor wafer
    Publication number: 20010031561
    Abstract: A method for minimizing the critical dimension growth of a feature on a semiconductor wafer includes performing an etch operation in a reactor 20 and controlling the temperature of the wafer 26 by controlling the pressure of the gas contacting the backside of the wafer 26 and/or providing a heat source 56 such as for example in the chuck 46 or electrode 28 associated with the wafer 26 in order to heat the wafer 26.
    Type: Application
    Filed: June 13, 2001
    Publication date: October 18, 2001
    Applicant: Tegal Corporation
    Inventors: Stephen P. DeOrnellas, Alferd Cofer, Leslie G. Jerde, Kurt A. Olson, Paritosh Rajora
  • Method and apparatus for etching a semiconductor wafer with features having vertical sidewalls
    Patent number: 6127277
    Abstract: A method and apparatus provide for etching a semiconductor wafer using a two step physical etching and a chemical etching process in order to create vertical sidewalls required for high density DRAMs and FRAMs.
    Type: Grant
    Filed: November 1, 1996
    Date of Patent: October 3, 2000
    Assignee: Tegal Corporation
    Inventors: Stephen P. DeOrnellas, Alferd Cofer, Paritosh Rajora
  • Method for minimizing the critical dimension growth of a feature on a semiconductor wafer
    Patent number: 6046116
    Abstract: A method for minimizing the critical dimension growth of a feature on a semiconductor wafer includes performing an etch operation in a reactor 20 and controlling the temperature of the wafer 26 by controlling the pressure of the gas contacting the backside of the wafer 26 and/or providing a heat source 56 such as for example in the chuck 46 or electrode 28 associated with the wafer 26 in order to heat the wafer 26.
    Type: Grant
    Filed: November 19, 1997
    Date of Patent: April 4, 2000
    Assignee: Tegal Corporation
    Inventors: Stephen P. DeOrnellas, Alfred Cofer, Leslie G. Jerde, Kurt A. Olson, Paritosh Rajora