Patents by Inventor Paritosh Vijay Kulkarni

Paritosh Vijay Kulkarni has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250111606
    Abstract: A fused bounding volume hierarchy, which is a combination of a base bounding volume hierarchy and one or more non-base bounding volume hierarchies, is generated. For each non-base bounding volume hierarchy, multiple subtrees in the non-base bounding volume hierarchy that include less than a threshold number of child nodes are identified. Each of these subtrees is then fused with the base bounding volume hierarchy at one of the nodes of the base bounding volume hierarchy, and an identifier of the level of detail for the non-base bounding volume hierarchy is included in the node. When displaying a scene or image, for a particular portion of the scene or image the level of detail to use is identified. The fused bounding volume hierarchy is traversed and the geometric objects in the nodes of the fused bounding volume hierarchy corresponding to the identified level of detail are displayed.
    Type: Application
    Filed: September 29, 2023
    Publication date: April 3, 2025
    Inventors: Paritosh Vijay Kulkarni, Ikeda Sho, Takahiro Harada
  • Patent number: 12198271
    Abstract: Devices and methods for multi-resolution geometric representation for ray tracing are described which include casting a ray in a space comprising objects represented by geometric shapes and approximating a volume of the geometric shapes using an accelerated hierarchy structure. The accelerated hierarchy structure comprises first nodes each representing a volume of one of the geometric shapes in the space and second nodes each representing an approximate volume of a group of the geometric shapes. When the ray is determined to intersect a bounding box of a second node representing one group of the geometric shapes, a selection is made between traversal and non-traversal of other second nodes based on a LOD for representing the volume of the one group of geometric shapes.
    Type: Grant
    Filed: September 28, 2022
    Date of Patent: January 14, 2025
    Assignees: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Sho Ikeda, Paritosh Vijay Kulkarni, Takahiro Harada
  • Publication number: 20240104844
    Abstract: Devices and methods for multi-resolution geometric representation for ray tracing are described which include casting a ray in a space comprising objects represented by geometric shapes and approximating a volume of the geometric shapes using an accelerated hierarchy structure. The accelerated hierarchy structure comprises first nodes each representing a volume of one of the geometric shapes in the space and second nodes each representing an approximate volume of a group of the geometric shapes. When the ray is determined to intersect a bounding box of a second node representing one group of the geometric shapes, a selection is made between traversal and non-traversal of other second nodes based on a LOD for representing the volume of the one group of geometric shapes.
    Type: Application
    Filed: September 28, 2022
    Publication date: March 28, 2024
    Applicants: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Sho Ikeda, Paritosh Vijay Kulkarni, Takahiro Harada