Patents by Inventor Parivesh Choudhary

Parivesh Choudhary has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • AUTOMATED TRANSLATION OF DESIGN SPECIFICATIONS OF ELECTRONIC CIRCUITS
    Publication number: 20250068846
    Abstract: Embodiments relate to a system for translating design specifications of an electronic circuit. In one embodiment, the design specification is parsed to identify one or more sentences. From the one or more identified sentences, the system extracts semantic concepts. Additionally, for each sentence of the one or more identified sentences, the system determines whether the sentence is translatable. If a target sentence is translatable, the system generates a parse tree for the target sentence, and generates a probabilistic shift-reduce schedule for the generated parse tree. Using the generated probabilistic shift-reduce schedule and optionally the generated parse tree, the system generates code for verifying the condition specified in the target sentence. In some embodiments, to generate the code, the system parses the target sentence using the generated probabilistic shift-reduce schedule.
    Type: Application
    Filed: November 8, 2024
    Publication date: February 27, 2025
    Inventors: Ganapathy Parthasarathy, Saurav Nanda, Parivesh Choudhary, Pawan Patil, Arun Venkatachar
  • Automated translation of design specifications of electronic circuits
    Patent number: 12175191
    Abstract: Embodiments relate to a system for translating design specifications of an electronic circuit. In one embodiment, the design specification is parsed to identify one or more sentences. From the one or more identified sentences, the system extracts semantic concepts. Additionally, for each sentence of the one or more identified sentences, the system determines whether the sentence is translatable. If a target sentence is translatable, the system generates a parse tree for the target sentence, and generates a probabilistic shift-reduce schedule for the generated parse tree. Using the generated probabilistic shift-reduce schedule and optionally the generated parse tree, the system generates code for verifying the condition specified in the target sentence. In some embodiments, to generate the code, the system parses the target sentence using the generated probabilistic shift-reduce schedule.
    Type: Grant
    Filed: November 15, 2021
    Date of Patent: December 24, 2024
    Assignee: Synopsys, Inc.
    Inventors: Ganapathy Parthasarathy, Saurav Nanda, Parivesh Choudhary, Pawan Patil, Arun Venkatachar
  • AUTOMATED TRANSLATION OF DESIGN SPECIFICATIONS OF ELECTRONIC CIRCUITS
    Publication number: 20220171932
    Abstract: Embodiments relate to a system for translating design specifications of an electronic circuit. In one embodiment, the design specification is parsed to identify one or more sentences. From the one or more identified sentences, the system extracts semantic concepts. Additionally, for each sentence of the one or more identified sentences, the system determines whether the sentence is translatable. If a target sentence is translatable, the system generates a parse tree for the target sentence, and generates a probabilistic shift-reduce schedule for the generated parse tree. Using the generated probabilistic shift-reduce schedule and optionally the generated parse tree, the system generates code for verifying the condition specified in the target sentence. In some embodiments, to generate the code, the system parses the target sentence using the generated probabilistic shift-reduce schedule.
    Type: Application
    Filed: November 15, 2021
    Publication date: June 2, 2022
    Inventors: Ganapathy Parthasarathy, Saurav Nanda, Parivesh Choudhary, Pawan Patil, Arun Venkatachar