Patents by Inventor Parixit Laljibhai AGHERA

Parixit Laljibhai AGHERA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10539997
    Abstract: The disclosure generally relates to a memory power reduction scheme that can flexibly transition memory blocks among different power states to reduce power consumption (especially with respect to leakage power) in a manner that balances tradeoffs between reduced power consumption and performance impacts. For example, according to various aspects, individual memory blocks may be associated with an access-dependent age, whereby memory blocks that are not accessed may be periodically aged. As such, in response to the age associated with a memory block crossing an appropriate threshold, the memory block may be transitioned to a power state that generally consumes less leakage power and has a larger performance penalty. Furthermore, one or more performance-related criteria may be defined with certain memory blocks to prevent and/or automatically trigger a transition to another power state.
    Type: Grant
    Filed: September 2, 2016
    Date of Patent: January 21, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Giby Samson, Parixit Laljibhai Aghera, Adam Edward Newham
  • Publication number: 20180067539
    Abstract: The disclosure generally relates to a memory power reduction scheme that can flexibly transition memory blocks among different power states to reduce power consumption (especially with respect to leakage power) in a manner that balances tradeoffs between reduced power consumption and performance impacts. For example, according to various aspects, individual memory blocks may be associated with an access-dependent age, whereby memory blocks that are not accessed may be periodically aged. As such, in response to the age associated with a memory block crossing an appropriate threshold, the memory block may be transitioned to a power state that generally consumes less leakage power and has a larger performance penalty. Furthermore, one or more performance-related criteria may be defined with certain memory blocks to prevent and/or automatically trigger a transition to another power state.
    Type: Application
    Filed: September 2, 2016
    Publication date: March 8, 2018
    Inventors: Giby SAMSON, Parixit Laljibhai AGHERA, Adam Edward NEWHAM
  • Publication number: 20170049376
    Abstract: Disclosed are techniques for determining a severity of motion disorder symptoms by receiving sensor data from one or more sensors, determining that the sensor data represents one or more activities of daily life (ADLs) of a user, assigning one or more probabilities to the one or more determined ADLs, each probability of the one or more probabilities indicating a confidence level that the sensor data represents a corresponding ADL, and providing the sensor data and the one or more probabilities to a motion disorder symptom scoring module that generates one or more scores for the one or more determined ADLs based on the sensor data, each score of the one or more scores indicating the severity of the motion disorder symptoms for a corresponding ADL, and combines the one or more scores and the one or more probabilities to generate an aggregated severity score for the motion disorder symptoms.
    Type: Application
    Filed: August 16, 2016
    Publication date: February 23, 2017
    Inventors: Jin Won LEE, Xinzhou WU, Parixit Laljibhai AGHERA, Rashid Ahmed Akbar ATTAR