Abstract: There is provided a proactive routing system and method. In some embodiments, the method includes determining slack for a net in a netlist, applying a routing condition to the net, calculating an extra delay related to the routing condition, determining a criticality of the net considering the extra delay and the determined slack, and setting a soft constraint based at least partially on the criticality.

Abstract: Routing systems and methods are provided having various strategies for optimizing and evaluating possible routes for netlist connections. In one embodiment, a data structure or matrix provides cost related data weighted to evaluate the impact proposed a connection or segment will have upon an attribute of interest such as, for example, speed, manufacturability or noise tolerance. This cost information can be related to terrain costs as well as shape costs to provide multidimensional cost information for connections. Processing such higher information cost data is made more efficient with an additive process that is less demanding than a computationally intensive iterative multiplication process. Various methods are also disclosed for shifting and adjusting routing grids to improve use of available space or reduce run time in routing.

Abstract: Routing systems and methods are provided having various strategies for optimizing and evaluating possible routes for netlist connections. In one embodiment, a data structure or matrix provides cost related data weighted to evaluate the impact proposed a connection or segment will have upon an attribute of interest such as, for example, speed, manufacturability or noise tolerance. This cost information can be related to terrain costs as well as shape costs to provide multidimensional cost information for connections. Processing such higher information cost data is made more efficient with an additive process that is less demanding than a computationally intensive iterative multiplication process. Various methods are also disclosed for shifting and adjusting routing grids to improve use of available space or reduce run time in routing.

Abstract: Routing systems and methods are provided having various strategies for optimizing and evaluating possible routes for netlist connections. In one embodiment, a data structure or matrix provides cost related data weighted to evaluate the impact proposed a connection or segment will have upon an attribute of interest such as, for example, speed, manufacturability or noise tolerance. This cost information can be related to terrain costs as well as shape costs to provide multidimensional cost information for connections. Processing such higher information cost data is made more efficient with an additive process that is less demanding than a computationally intensive iterative multiplication process. Various methods are also disclosed for shifting and adjusting routing grids to improve use of available space or reduce run time in routing.

Abstract: Routing systems and methods are provided having various strategies for optimizing and evaluating possible routes for netlist connections. In one embodiment, a data structure or matrix provides cost related data weighted to evaluate the impact proposed a connection or segment will have upon an attribute of interest such as, for example, speed, manufacturability or noise tolerance. This cost information can be related to terrain costs as well as shape costs to provide multidimensional cost information for connections. Processing such higher information cost data is made more efficient with an additive process that is less demanding than a computationally intensive iterative multiplication process. Various methods are also disclosed for shifting and adjusting routing grids to improve use of available space or reduce run time in routing.

Abstract: Routing systems and methods are provided having various strategies for optimizing and evaluating possible routes for netlist connections. In one embodiment, a data structure or matrix provides cost related data weighted to evaluate the impact proposed a connection or segment will have upon an attribute of interest such as, for example, speed, manufacturability or noise tolerance. This cost information can be related to terrain costs as well as shape costs to provide multidimensional cost information for connections. Processing such higher information cost data is made more efficient with an additive process that is less demanding than a computationally intensive iterative multiplication process. Various methods are also disclosed for shifting and adjusting routing grids to improve use of available space or reduce run time in routing.

Abstract: A method of broadcasting N, an even integer, bits of data onto a bus that includes a first plurality of electrical conductors and a second plurality of electrical conductors. The method includes: broadcasting a first portion of data that includes N/2 bits of data onto the first plurality of electrical conductors. Then, after a time period has elapsed that is greater than 0 seconds and less than the time period required to transfer 2 bits of data sequentially on one of the first plurality of electrical conductors, broadcasting a second portion of data that includes N/2 bits of data onto the second plurality of electrical conductors.

Abstract: A system that facilitates generating a global routing for a layout of an integrated circuit operates by receiving a netlist to be routed. The system partitions this netlist into global signals, datapath signals, and control signals. Next, the system creates a tiling grid of the integrated circuit and routes connection nets between tiles within this grid. The system then selects an area within the integrated circuit larger than a tile in the first grid. The system creates a second grid of tiles smaller than the tiles of the first grid within this selected area. During this process, connection nets are routed between tiles on the second grid while routings within the first grid are maintained. The system merges connection nets within the first grid with connection nets within the second grid to form the global routing.

Abstract: Provided is a data structure containing wiring information for an integrated circuit and a method for storing the same in a computer readable medium. In one embodiment of the present invention storage of the data structure is achieved by mapping said integrated circuit into memory locations of said medium as a wiring plane having a plurality of data points arranged in a grid. Each of the plurality of data points having state information associated therewith, which includes a plurality of attributes. Subsections of the grid are associated with memory locations in the computer readable medium to form a plurality of tiles. Specifically the tiles and data points are arranged so that a sub-portion of the data points associated with one of the plurality of tiles have common attributes.

Abstract: A system that facilitates generating a global routing for a layout of an integrated circuit operates by receiving a netlist to be routed. The system partitions this netlist into global signals, datapath signals, and control signals. Next, the system creates a tiling grid of the integrated circuit and routes connection nets between tiles within this grid. The system then selects an area within the integrated circuit larger than a tile in the first grid. The system creates a second grid of tiles smaller than the tiles of the first grid within this selected area. During this process, connection nets are routed between tiles on the second grid while routings within the first grid are maintained. The system merges connection nets within the first grid with connection nets within the second grid to form the global routing.

Abstract: Provided is a data structure containing wiring information for an integrated circuit and a method for storing the same in a computer readable medium. In one embodiment of the present invention storage of the data structure is achieved by mapping said integrated circuit into memory locations of said medium as a wiring plane having a plurality of data points arranged in a grid. Each of the plurality of data points having state information associated therewith, which includes a plurality of attributes. Subsections of the grid are associated with memory locations in the computer readable medium to form a plurality of tiles. Specifically the tiles and data points are arranged so that a sub-portion of the data points associated with one of the plurality of tiles have common attributes.

Abstract: A method of broadcasting N, an even integer, bits of data onto a bus that includes a first plurality of electrical conductors and a second plurality of electrical conductors. The method includes: broadcasting a first portion of data that includes N/2 bits of data onto the first plurality of electrical conductors. Then, after a time period has elapsed that is greater than 0 seconds and less than the time period required to transfer 2 bits of data sequentially on one of the first plurality of electrical conductors, broadcasting a second portion of data that includes N/2 bits of data onto the second plurality of electrical conductors.

Abstract: An automated method and system for designing an integrated circuit are disclosed which construct an initial substrate layout of the integrated circuit in response to receipt of a high-level functional description of an integrated circuit. The initial substrate layout, which includes a number of subcircuits electrically connected by a number of interconnects, is constructed based upon estimated timing characteristics of the subcircuits. Next, particular subcircuits are arranged to optimize performance of the substrate layout of the integrated circuit. Performance characteristics of the substrate layout, including timing characteristics of the number of subcircuits and resistive and capacitive characteristics of the number of interconnects, are then determined. In response to a determination of the performance characteristics of the substrate layout, operating power levels of selected subcircuits and resistances of selected interconnects are adjusted to optimize performance of the substrate layout.

Abstract: In accordance with the teachings of this invention a method for positioning components of input/output circuits is provided. These components are positioned on a semiconductor substrate. The semiconductor substrate includes other than input/output circuits. Each input/output circuit is provided for processing a single bit of information within a data word containing multiple bits. The method includes the step of (1) dividing each input/output circuit into groups containing similar functional subcomponents; (2) forming a vertical column of subcomponents for each input/output circuit and connecting these subcomponents to perform the function; (3) placing said columns in adjacency to form a plurality of columns with like subcomponents immediately adjacent to each other forming row groups of said like subcomponents; and (4) forming guard rings around the subcomponent row groups if required. Also in accordance with this invention, a group of input/output circuits is provided.

Abstract: In accordance with the teachings of this invention a method for positioning components of input/output circuits is provided. These components are positioned on a semiconductor substrate. The semiconductor substrate includes other than input/output circuits. Each input/output circuit is provided for processing a single bit of information within a data word containing multiple bits. The method includes the step of (1) dividing each input/output circuit into groups containing similar functional subcomponents; (2) forming a vertical column of subcomponents for each input/output circuit and connecting these subcomponents to perform the function; (3) placing said columns in adjacency to form a plurality of columns with like subcomponents immediately adjacent to each other other forming row groups of said like subcomponents; and (4) forming at least one guard ring around the subcomponent row groups.Also in accordance with this invention, a group of input/output circuits is provided.

Abstract: A saturation-limited bipolar transistor device or circuit and a method of making same are provided which includes a merged NPN transistor and a PNP transistor structure formed so as to produce denser cells or circuits. A simple process is used to form the structure which includes a double diffused technique for making the PNP transistor. The PNP transistor has a double diffused emitter-base arrangement wherein the emitter is asymmetrically positioned with respect to the base so as to also serve as a contact for the base of the NPN transistor. The PNP transistor limits the input current by bypassing excess current to a silicon semiconductor substrate or chip. The structure includes an N type epitaxial layer formed on an N type subcollector with a P type region provided near the surface of the epitaxial layer. The epitaxial layer serves as the NPN collector and as the PNP base contact region.

Abstract: A saturation-limited bipolar transistor device or circuit and a method of making same are provided which includes a merged NPN transistor and a PNP transistor structure formed so as to produce denser cells or circuits. A simple process is used to form the structure which includes a double diffused technique for making the PNP transistor. The PNP transistor has a double diffused emitter-base arrangement wherein the emitter is asymmetrically positioned with respect to the base so as to also serve as a contact for the base of the NPN transistor. The PNP transistor limits the input current by bypassing excess current to a silicon semiconductor substrate or chip. The structure includes an N type epitaxial layer formed on an N type subcollector with a P type region provided near the surface of the epitaxial layer. The epitaxial layer serves as the NPN collector and as the PNP base contact region.

Abstract: This invention provides improved non-volatile semiconductor memories which include a one device dynamic volatile memory circuit having a storage capacitor with a plate and a storage node coupled to a non-volatile device having a floating gate, a control gate and a voltage divider having first and second serially-connected capacitors, with the floating gate being disposed at the common point between the first and second capacitors. The plate of the storage capacitor is connected to a reference voltage source. The control gate is preferably capacitively coupled to the floating gate through the first capacitor which includesa dual charge or electron injector structure. The capacitance of the first capacitor has a value substantially less than that of the second capacitor.