Patents by Inventor Parth Saurabhkumar Shah

Parth Saurabhkumar Shah has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250231896
    Abstract: In some aspects, a system may transmit, via a main device of the system, a first value of a chip select signal indicating chip select de-assertion. The system may transmit, via a target device of the system, an interrupt signal while the chip select line indicates the first value. The system may transmit, via the main device and via the chip select line, a second value of the chip select signal indicating chip select assertion. The system may perform, via at least one of the one or more data lines, one or more data operations based on the target device transmitting the interrupt signal. Numerous other aspects are described.
    Type: Application
    Filed: January 11, 2024
    Publication date: July 17, 2025
    Inventors: Parth Saurabhkumar SHAH, Amit GIL
  • Publication number: 20250110667
    Abstract: A memory device may respond to two types of read commands. When the memory device receives a first type of read command, the memory device may read data from a memory array beginning at an address indicated in association with the received read command. When the memory device receives a second type of read command, the memory device may begin reading data from a cache in the memory device. Data that is read from the memory array may also be stored in the cache.
    Type: Application
    Filed: September 28, 2023
    Publication date: April 3, 2025
    Inventor: Parth Saurabhkumar SHAH
  • Patent number: 11886369
    Abstract: Methods and apparatuses directed to more efficient data transfers within die architectures. In some examples, a die package includes controller logic electrically coupled to a first communication bus and a second communication bus. The controller logic can receive an initial data transfer request over the first communication bus, and determine a final address of the initial data transfer request. Further, the controller logic can assert a chip select signal of the second communication bus to initiate a data exchange. While asserting the chip select signal, the controller logic can receive an additional data transfer request over the first communication bus, and determine an initial address of the additional data transfer request. Based on the determined initial and final addresses, the controller logic can initiate an additional data exchange over the second communication bus without de-asserting the chip select signal.
    Type: Grant
    Filed: September 14, 2023
    Date of Patent: January 30, 2024
    Assignee: QUALCOMM Incorporated
    Inventors: Parth Saurabhkumar Shah, Imran Ghazi, Philip Hardy