Abstract: A memory device may respond to two types of read commands. When the memory device receives a first type of read command, the memory device may read data from a memory array beginning at an address indicated in association with the received read command. When the memory device receives a second type of read command, the memory device may begin reading data from a cache in the memory device. Data that is read from the memory array may also be stored in the cache.

Abstract: Methods and apparatuses directed to more efficient data transfers within die architectures. In some examples, a die package includes controller logic electrically coupled to a first communication bus and a second communication bus. The controller logic can receive an initial data transfer request over the first communication bus, and determine a final address of the initial data transfer request. Further, the controller logic can assert a chip select signal of the second communication bus to initiate a data exchange. While asserting the chip select signal, the controller logic can receive an additional data transfer request over the first communication bus, and determine an initial address of the additional data transfer request. Based on the determined initial and final addresses, the controller logic can initiate an additional data exchange over the second communication bus without de-asserting the chip select signal.