Abstract: Systems and methods for providing metric data for patterns in a modeling environment are disclosed. In some aspects, contexts for generating metric data for a pattern are constructed. The pattern represents one or more computations executable in the modeling environment and associated with operation or behavior of a real-world system. The contexts include information about the pattern. The metric data is associated with one or more objectives with which the use of the pattern is associated. Code for the pattern for each context is generated. Metric data is generated for the pattern and under each context. The metric data of the pattern under each context is associated with the objectives. The metric data and the association are stored for use in providing information about or based on the metric data when the pattern is to be or is used in a model representing the real-world system.

Abstract: Systems and methods for providing metric data for patterns in a modeling environment are disclosed. In some aspects, contexts for generating metric data for a pattern are constructed. The pattern represents one or more computations executable in the modeling environment and associated with operation or behavior of a real-world system. The contexts include information about the pattern. The metric data is associated with one or more objectives with which the use of the pattern is associated. Code for the pattern for each context is generated. Metric data is generated for the pattern and under each context. The metric data of the pattern under each context is associated with the objectives. The metric data and the association are stored for use in providing information about or based on the metric data when the pattern is to be or is used in a model representing the real-world system.

Abstract: Systems and methods for providing metric data for patterns in a modeling environment are disclosed. In some aspects, contexts for generating metric data for a pattern are constructed. The pattern represents one or more computations executable in the modeling environment and associated with operation or behavior of a real-world system. The contexts include information about the pattern. The metric data is associated with one or more objectives with which the use of the pattern is associated. Code for the pattern for each context is generated. Metric data is generated for the pattern and under each context. The metric data of the pattern under each context is associated with the objectives. The metric data and the association are stored for use in providing information about or based on the metric data when the pattern is to be or is used in a model representing the real-world system.

Abstract: A device is configured to receive delay information associated with a model including a set of model elements and one or more delay elements. The delay information may identify a model element, of the set of model elements, and a quantity of delay to be associated with the model element. The model may be associated with a total quantity of delay. The device is configured to determine accumulated delay information based on the model, and to determine a set of retiming values associated with the set of model elements. The device is configured to redistribute the one or more delay elements associated with the model, based on the set of retiming values, to satisfy the quantity of delay to be associated with the model element, and to maintain the total quantity of delay associated with the model. The device is configured to provide the redistributed model.

Abstract: A system and method evaluates power information for a high-level model to be implemented in target hardware, and performs one or more power-reducing transmutations on the model. Transmutations may include moving one or more components from a fast rate region to a slow rate region, reducing bit width of data, signals, or other values, and replacing multiple instances of a resource with a shared instance of the resource. An in-memory representation of the model may be generated that reduces the model to a plurality of core components. A power score evaluation engine may assign power scores to the core components. Power scores may be retrieved from one or more power score database. The power scores may be non-dimensional scores representing power consumption relationships among the core components, and be target independent. Hints or alerts regarding suggested changes to the model to optimize power consumption may be presented to a user. A revised model incorporating the suggested changes may be constructed.

Abstract: A device receives a model, in a technical computing environment, that includes blocks and lines, and determines an application domain associated with the model. The device determines code generation optimizations for the model, determines dependencies of the code generation optimizations, and determines performance characteristics for the device. The device determines capabilities of a target compiler for the code generated based on the model, and determines a profile for target hardware to be used to execute the code. The device identifies an order for the code generation optimizations based on the determined information, generates optimal code for the model based on the identified order for the code generation optimizations, and outputs and/or store the optimal code.

Abstract: A device is configured to receive optimization information associated with a model, determine an amount of delay to be inserted into the model, and determine a sampling factor by which a first data rate associated with a signal is to be modified into a second data rate. The device is configured to determine a region of interest, insert an upsampling block that upsamples the signal entering the region of interest based on the sampling factor, and insert a downsampling block, associated with a unit of delay, which downsamples the signal exiting the region of interest based on the sampling factor. The device is configured to convert the unit of delay into a fast delay block, corresponding to the amount of delay, and insert the fast delay block in the region of interest. The device is configured to generate code associated with the model, and provide the code.

Abstract: A system for facilitating system design includes a back-annotation tool that annotates a model of a hardware system with information derived from results of synthesizing the model to the target hardware description. The derived information may include timing information, information about area usage, power consumption, etc. The derived information may be displayed in conjunction with the model in a modeling environment.

Abstract: A device receives a model that includes blocks and lines provided between the blocks, and identifies first candidate boundaries for the model. Each of the first candidate boundaries defines a group of blocks. The device generates an intermediate representation (IR) of the model, performs an optimization of the IR to generate an optimized IR, and identifies second candidate boundaries for the model based on the optimized IR. Each of the second candidate boundaries defines a group of blocks, and the first and second candidate boundaries define a set of candidate boundaries. The device reduces the set of candidate boundaries, to a reduced set of boundaries, based on code efficiency metrics or metrics associated with a hardware platform. The device generates code for the model based on the reduced set of boundaries, and outputs the code.

Abstract: A system and method automatically inserts pipelines into a high-level program specification. An Intermediate Representation (IR) builder creates one or more graphs or trees based on the high-level program specification. A scheduler iteratively applies a bounded scheduling algorithm to produce an execution schedule for the IR minimizing overall execution time for a given number of pipeline stages. A Hardware Description Language (HDL) code generator may utilize the pipelined, scheduled IR to generate optimized HDL code corresponding to the high-level program specification. An annotated version of the high-level program specification showing where the pipelines have been inserted may be displayed allowing additional design exploration.

Abstract: A system and method automatically inserts pipelines into a high-level program specification. An Intermediate Representation (IR) builder creates one or more graphs or trees based on the high-level program specification. A scheduler iteratively applies a bounded scheduling algorithm to produce an execution schedule for the IR minimizing overall execution time for a given number of pipeline stages. A Hardware Description Language (HDL) code generator may utilize the pipelined, scheduled IR to generate optimized HDL code corresponding to the high-level program specification. An annotated version of the high-level program specification showing where the pipelines have been inserted may be displayed allowing additional design exploration.

Abstract: Embodiments relate to a system and method for identifying common patterns of use of resources. The resource usage patterns may be specified using a tree structure, and identifying common resource use patterns may involve identifying isomorphic subtrees between two or more trees. Isomorphic subtree identification may be accomplished by converting trees into key-based representation and analyzing the key-based representation to identify common patterns within the key-based representation.

Abstract: Instruction Set Extensions (ISEs) can be used effectively to accelerate the performance of embedded processors. The critical, and difficult task of ISE selection is often performed manually by designers. A few automatic methods for ISE generation have shown good capabilities, but are still limited in the handling of memory accesses, and so they fail to directly address the memory wall problem. We present here the first ISE identification technique that can automatically identify state-holding Application-specific Functional Units (AFUs) comprehensively, thus being able to eliminate a large portion of memory traffic from cache and main memory. Our cycle-accurate results obtained by the SimpleScalar simulator show that the identified AFUs with architecturally visible storage gain significantly more than previous techniques, and achieve an average speedup of 2.8× over pure software execution.

Abstract: Instruction Set Extensions (ISEs) can be used effectively to accelerate the performance of embedded processors. The critical, and difficult task of ISE selection is often performed manually by designers. A few automatic methods for ISE generation have shown good capabilities, but are still limited in the handling of memory accesses, and so they fail to directly address the memory wall problem. We present here the first ISE identification technique that can automatically identify state-holding Application-specific Functional Units (AFUs) comprehensively, thus being able to eliminate a large portion of memory traffic from cache and main memory. Our cycle-accurate results obtained by the SimpleScalar simulator show that the identified AFUs with architecturally visible storage gain significantly more than previous techniques, and achieve an average speedup of 2.8× over pure software execution.