Abstract: A method includes receiving a first device wafer comprising a plurality of dies, bonding a first side of a temporary wafer to a first side of the first device wafer to form a combined wafer, and performing a first patterning process on the combined wafer to form first trenches in the combined wafer. The first trenches fully extend through the first device wafer and partially into the temporary wafer from the first side of the temporary wafer. The first trenches separate the plurality of dies from each other. The method further includes placing the combined wafer on a support and applying a force to the combined wafer to separate the temporary wafer into individual temporary regions. Each individual temporary region is bonded to a respective individual die. The method further includes attaching individual dies to a second device wafer and removing the individual temporary regions from the individual dies.

Abstract: Structures and methods are disclosed in which a layer stack can be formed with a plurality of layers of a metal, where each of the layers of metal can be separated by a layer of a dielectric. An opening in the layer stack can be formed such that a semiconductor layer beneath the plurality of layers of the metal is uncovered. One or more vertical channel structures can be formed within the opening by epitaxial growth. The vertical channel structure can include a vertically oriented transistor. The vertical channel structure can include an interface of a silicide metal with a first metal layer of the plurality of metal layers. The interface can correspond to one of a source or a drain connection of a transistor. The silicide metal can be annealed above a temperature threshold to form a silicide interface between the vertical channel structure and the first metal layer.

Abstract: Methods for the manufacture of semiconductor devices constructed with two-dimensional (2D) materials and conductive oxides using three-dimensional (3D) nanosheets are disclosed. Aspects can include forming the stack of layers comprising a first layer of a semiconductive-behaving material separated from a base layer by a first layer of a first dielectric material and a first layer of a second dielectric material; a second layer of the semiconductive-behaving material separated from the first layer of the semiconductive-behaving material by a second layer of the second dielectric material; and a second layer of the second dielectric material formed on the second layer of the semiconductive-behaving material. Aspects include forming a metal contact coupled with the semiconductive-behaving material, forming a 2D material on the semiconductive-behaving material, forming a layer of a high-k dielectric material on the 2D material, and forming a gate metal on the high-k dielectric material.

Abstract: A method of microfabrication includes epitaxially growing a first vertical channel structure of silicon-containing material on a first sacrificial layer of silicon containing material, the first sacrificial layer having etch selectivity with respect to the vertical channel structure. A core opening is directionally etched through the vertical channel structure to expose the first sacrificial layer, and the first sacrificial layer is isotropically etched through the core opening to form a first isolation opening for isolating the first vertical channel structure.

Abstract: Three-dimensional (3D) memory structures and methods to manufacture 3D memory structures are disclosed. A method includes forming a stack of layers including a first sub-stack for a first transistor structure, comprised of a first conductive layer, a gate layer, and a second source/drain layer. The stack of layers can include a second sub-stack for a memory structure positioned on the first sub-stack, the second sub-stack including at least one layer of conductive material and at least one layer of non-conductive material, and a third sub-stack for a second transistor structure. The method includes forming a channel opening in the stack of layers, providing a first channel structure within the channel opening, forming a memory dielectric layer in the channel opening and aligned with the memory structure, and providing a second channel structure in the channel opening in contact with the memory dielectric layer and aligned with the second transistor structure.

Abstract: Apparatuses, devices, and methods for fabricating one or more vertically integrated single bit capacitor-based memory cells is disclosed. A single bit capacitor-based memory cell can include a vertically oriented transistor and a vertically oriented capacitor that is vertically integrated with the transistor, so as to form a memory cell. Aspects of the disclosure include process steps for forming the transistor and the capacitor, including a first metal part of a capacitor, a second metal part of a capacitor and an electrically insulating layer disposed between the two. The transistor and the capacitor also include an electrical contact between them and a layer that insulates the transistor from the base layer or the underlying substrate.

Abstract: A method of fabricating a semiconductor device includes forming a patterned stack of layers including at least one lower active layer for forming a lower transistor and at least one upper active layer for forming an upper transistor stacked on the lower transistor. A dummy gate is formed surrounding a gate portion of each of the lower active layers and each of the upper active layers in the patterned stack, and the source-drain portions of the lower active layers and the upper active layers are doped. Source-drain connections to doped source-drain portions of the lower active layers and the upper active layers are formed. The dummy gate of the lower active layers and the upper active layers is replaced with a gate-all-around (GAA) structure to form the lower transistor and the upper transistor.

Abstract: Methods for the manufacture of three-dimensional (3D) semiconductor devices are disclosed. Aspects can include forming a patterned first conductive source/drain structure of a transistor structure, forming a gate patterned conductive structure of the transistor structure separated from the first conductive source/drain structure by at least one dielectric layer, forming a patterned second conductive source/drain structure of the transistor structure separated from the gate patterned conductive structure by at least one dielectric layer, forming a transistor body opening extending through the transistor structure, forming a gate dielectric in the transistor body opening, and forming a material in the transistor body opening extending from the patterned first conductive source/drain structure to the patterned second conductive source/drain structure.

Abstract: A semiconductor device includes a substrate having a working surface and a transistor formed in the substrate. The transistor includes a complex channel structure including a main portion extending in a main direction along the working surface, and tail portions each connected to a respective end of the main portion and extending along the working surface in a different direction from the main direction, a distal end of each tail portion including a source-drain (S-D) end such that the S-D ends are offset from the main portion of the complex channel structure. A gate all around (GAA) structure formed around only the main portion of the complex channel structure between the tail portions, and S-D contacts formed on respective S-D ends of the complex channel structure such that the S-D contacts are offset from the GAA structure.

Abstract: Apparatuses, devices and methods for fabricating one or more vertically integrated single bit capacitor-based memory cells is disclosed. A single bit capacitor-based memory cell can include a vertically oriented transistor and a vertically oriented capacitor that is vertically integrated with the transistor, so as to form a memory cell. Aspects of the disclosure include process steps for forming the transistor and the capacitor, including a first metal part of a capacitor, a second metal part of a capacitor and an electrically insulating layer disposed between the two. The transistor and the capacitor also include an electrical contact between them and a layer that insulates the transistor from the base layer or the underlying substrate.

Abstract: A method includes forming a fin structure over a substrate, the fin structure including alternating first semiconductor layers and second semiconductor layers stacked along a vertical direction; forming a dummy gate structure over the fin structure; selectively depositing an outer spacer layer on the dummy gate structure; performing a plasma doping process to form source/drain regions in each second semiconductor layer adjacent the dummy gate structure, where a portion of each second semiconductor layer interposing between the source/drain regions defines a channel region; forming a dielectric layer over the fin structure; removing the dummy gate structure to form a gate trench in the dielectric layer; selectively removing the first semiconductor layers to form openings interleaved with the second semiconductor layers; and forming a metal gate structure to fill the gate trench and the openings.

Abstract: A method includes forming a fin structure over a substrate, the fin structure including alternating first semiconductor layers and second semiconductor layers stacked along a vertical direction; forming a dummy gate structure over the fin structure; performing a plasma doping process to form source/drain regions in each second semiconductor layer adjacent the dummy gate structure, where a portion of each second semiconductor layer interposing between the source/drain regions defines a channel region; forming a dielectric layer over the fin structure; removing the dummy gate structure to form a gate trench in the dielectric layer; selectively removing the first semiconductor layers to form openings interleaved with the second semiconductor layers; depositing an inner spacer layer to partially fill the gate trench and the openings, wherein the inner spacer layer overlaps with the source/drain regions along the lateral direction; and forming a metal gate structure over the inner spacer layer.

Abstract: According to an aspect of the disclosure, a semiconductor device is provided. The semiconductor device includes a stack of insulating layers and interconnect layers that are positioned alternatingly over a substrate. The semiconductor device includes a channel structure extending from the substrate and further through the insulating layers and the interconnect layers. The channel structure includes a first channel section positioned over the substrate and coupled to a first group of the interconnect layers, and a second channel section positioned over the first channel section and coupled to a second group of the interconnect layers. The semiconductor device also includes a plurality of contact structures extending from and coupled to the interconnect layers in a staircase configuration such that each of the plurality of contact structures extends from a respective interconnect layer.

Abstract: A semiconductor device may include a transistor structure. The transistor structure may include a metal structure extending along a vertical direction; a gate dielectric layer around the metal structure; a channel layer around the gate dielectric layer; a first metal electrode disposed below the metal structure and in electrical contact with a first end of the channel layer; a second metal electrode disposed above the metal structure and in electrical contact with a second end of the channel layer; and a third metal electrode disposed above and in electrical contact with the metal structure.

Abstract: Structures and methods of semiconductor transistor structure include a first source/drain contact of a transistor and a dielectric structure formed on top of the first source/drain contact. A gate electrode of the transistor can be formed on top of the dielectric structure. A gate dielectric can include a first part formed vertically along at least a first sidewall of the gate electrode and a second part formed vertically along at least a second sidewall of the gate electrode. A channel of the transistor can include a first part formed on a surface of the first part of the gate dielectric and a second part formed on a surface of the second part of the gate dielectric. A second source/drain contact of the transistor can include a first part on top of the first part of the channel and a second part on top of the second part of the channel.

Abstract: A semiconductor device may include a transistor structure. The transistor structure may include a metal structure extending along a vertical direction; a gate dielectric layer around the metal structure; a channel layer around the gate dielectric layer; a first metal electrode disposed below the metal structure and in electrical contact with a first end of the channel layer; a second metal electrode disposed above the metal structure and in electrical contact with a second end of the channel layer; and a third metal electrode disposed above and in electrical contact with the metal structure.

Abstract: According to an aspect of the disclosure, a semiconductor device is provided. The semiconductor device includes a first bottom contact positioned in a dielectric layer over a substrate, and a first channel structure extending from and in contact with the first bottom contact in a vertical direction perpendicular to the substrate. The first channel structure includes a bottom portion over the first bottom contact, a middle portion over the bottom portion, and a top portion over the middle portion. The semiconductor device includes a first gate structure positioned around the middle portion of the first channel structure, and a first top contact positioned over and in contact with the top portion of the first channel structure.

Abstract: A semiconductor structure includes one or more first nanostructures extending along a first lateral direction; one or more second nanostructures extending along the first lateral direction and vertically disposed above the one or more first nanostructures; and a gate structure extending along a second lateral direction perpendicular to the first lateral direction, and disposed around each of the one or more first nanostructures and each of the one or more second nanostructures. The gate structure comprises: (i) a first metal material, (ii) a ferroelectric material, and (iii) a second metal material.

Abstract: Aspects of the present disclosure provide a semiconductor structure, which can include a lower transistor including a lower channel that is elongated horizontally and includes a lower doped first-type semiconductor layer of a lower doped semiconductor layer, an upper transistor vertically stacked over the lower transistor and including an upper channel that is elongated horizontally and includes an upper doped first-type semiconductor layer of an upper doped semiconductor layer, a lower capacitor electrically connected to and horizontally elongated from the lower transistor and including a first lower plate that includes a lower doped second-type semiconductor layer of the lower doped semiconductor layer, and an upper capacitor vertically stacked over the lower capacitor and electrically connected to and horizontally elongated from the upper transistor and including a first upper plate that includes an upper doped second-type semiconductor layer of the upper doped semiconductor layer.

Abstract: A semiconductor device includes a memory cell unit positioned over a substrate. The memory cell unit includes a transistor and a capacitor. The capacitor includes an inner conductor, a capacitor dielectric all around the inner conductor, an outer conductor all around the capacitor dielectric, and dielectric support structures below the inner conductor. The capacitor is elongated in a length direction parallel to a working surface of the substrate, and the dielectric support structures are spaced along the length direction. The transistor includes a channel structure, a gate structure all around the channel structure, and source/drain (S/D) regions on opposing ends of the channel structure.