Abstract: A semiconductor device includes a substrate having a working surface and a transistor formed in the substrate. The transistor includes a complex channel structure including a main portion extending in a main direction along the working surface, and tail portions each connected to a respective end of the main portion and extending along the working surface in a different direction from the main direction, a distal end of each tail portion including a source-drain (S-D) end such that the S-D ends are offset from the main portion of the complex channel structure. A gate all around (GAA) structure formed around only the main portion of the complex channel structure between the tail portions, and S-D contacts formed on respective S-D ends of the complex channel structure such that the S-D contacts are offset from the GAA structure.

Abstract: Apparatuses, devices and methods for fabricating one or more vertically integrated single bit capacitor-based memory cells is disclosed. A single bit capacitor-based memory cell can include a vertically oriented transistor and a vertically oriented capacitor that is vertically integrated with the transistor, so as to form a memory cell. Aspects of the disclosure include process steps for forming the transistor and the capacitor, including a first metal part of a capacitor, a second metal part of a capacitor and an electrically insulating layer disposed between the two. The transistor and the capacitor also include an electrical contact between them and a layer that insulates the transistor from the base layer or the underlying substrate.

Abstract: A method includes forming a fin structure over a substrate, the fin structure including alternating first semiconductor layers and second semiconductor layers stacked along a vertical direction; forming a dummy gate structure over the fin structure; selectively depositing an outer spacer layer on the dummy gate structure; performing a plasma doping process to form source/drain regions in each second semiconductor layer adjacent the dummy gate structure, where a portion of each second semiconductor layer interposing between the source/drain regions defines a channel region; forming a dielectric layer over the fin structure; removing the dummy gate structure to form a gate trench in the dielectric layer; selectively removing the first semiconductor layers to form openings interleaved with the second semiconductor layers; and forming a metal gate structure to fill the gate trench and the openings.

Abstract: A method includes forming a fin structure over a substrate, the fin structure including alternating first semiconductor layers and second semiconductor layers stacked along a vertical direction; forming a dummy gate structure over the fin structure; performing a plasma doping process to form source/drain regions in each second semiconductor layer adjacent the dummy gate structure, where a portion of each second semiconductor layer interposing between the source/drain regions defines a channel region; forming a dielectric layer over the fin structure; removing the dummy gate structure to form a gate trench in the dielectric layer; selectively removing the first semiconductor layers to form openings interleaved with the second semiconductor layers; depositing an inner spacer layer to partially fill the gate trench and the openings, wherein the inner spacer layer overlaps with the source/drain regions along the lateral direction; and forming a metal gate structure over the inner spacer layer.

Abstract: According to an aspect of the disclosure, a semiconductor device is provided. The semiconductor device includes a stack of insulating layers and interconnect layers that are positioned alternatingly over a substrate. The semiconductor device includes a channel structure extending from the substrate and further through the insulating layers and the interconnect layers. The channel structure includes a first channel section positioned over the substrate and coupled to a first group of the interconnect layers, and a second channel section positioned over the first channel section and coupled to a second group of the interconnect layers. The semiconductor device also includes a plurality of contact structures extending from and coupled to the interconnect layers in a staircase configuration such that each of the plurality of contact structures extends from a respective interconnect layer.

Abstract: Structures and methods of semiconductor transistor structure include a first source/drain contact of a transistor and a dielectric structure formed on top of the first source/drain contact. A gate electrode of the transistor can be formed on top of the dielectric structure. A gate dielectric can include a first part formed vertically along at least a first sidewall of the gate electrode and a second part formed vertically along at least a second sidewall of the gate electrode. A channel of the transistor can include a first part formed on a surface of the first part of the gate dielectric and a second part formed on a surface of the second part of the gate dielectric. A second source/drain contact of the transistor can include a first part on top of the first part of the channel and a second part on top of the second part of the channel.

Abstract: A semiconductor device may include a transistor structure. The transistor structure may include a metal structure extending along a vertical direction; a gate dielectric layer around the metal structure; a channel layer around the gate dielectric layer; a first metal electrode disposed below the metal structure and in electrical contact with a first end of the channel layer; a second metal electrode disposed above the metal structure and in electrical contact with a second end of the channel layer; and a third metal electrode disposed above and in electrical contact with the metal structure.

Abstract: A semiconductor device may include a transistor structure. The transistor structure may include a metal structure extending along a vertical direction; a gate dielectric layer around the metal structure; a channel layer around the gate dielectric layer; a first metal electrode disposed below the metal structure and in electrical contact with a first end of the channel layer; a second metal electrode disposed above the metal structure and in electrical contact with a second end of the channel layer; and a third metal electrode disposed above and in electrical contact with the metal structure.

Abstract: According to an aspect of the disclosure, a semiconductor device is provided. The semiconductor device includes a first bottom contact positioned in a dielectric layer over a substrate, and a first channel structure extending from and in contact with the first bottom contact in a vertical direction perpendicular to the substrate. The first channel structure includes a bottom portion over the first bottom contact, a middle portion over the bottom portion, and a top portion over the middle portion. The semiconductor device includes a first gate structure positioned around the middle portion of the first channel structure, and a first top contact positioned over and in contact with the top portion of the first channel structure.

Abstract: A semiconductor structure includes one or more first nanostructures extending along a first lateral direction; one or more second nanostructures extending along the first lateral direction and vertically disposed above the one or more first nanostructures; and a gate structure extending along a second lateral direction perpendicular to the first lateral direction, and disposed around each of the one or more first nanostructures and each of the one or more second nanostructures. The gate structure comprises: (i) a first metal material, (ii) a ferroelectric material, and (iii) a second metal material.

Abstract: Aspects of the present disclosure provide a semiconductor structure, which can include a lower transistor including a lower channel that is elongated horizontally and includes a lower doped first-type semiconductor layer of a lower doped semiconductor layer, an upper transistor vertically stacked over the lower transistor and including an upper channel that is elongated horizontally and includes an upper doped first-type semiconductor layer of an upper doped semiconductor layer, a lower capacitor electrically connected to and horizontally elongated from the lower transistor and including a first lower plate that includes a lower doped second-type semiconductor layer of the lower doped semiconductor layer, and an upper capacitor vertically stacked over the lower capacitor and electrically connected to and horizontally elongated from the upper transistor and including a first upper plate that includes an upper doped second-type semiconductor layer of the upper doped semiconductor layer.

Abstract: A semiconductor device includes a memory cell unit positioned over a substrate. The memory cell unit includes a transistor and a capacitor. The capacitor includes an inner conductor, a capacitor dielectric all around the inner conductor, an outer conductor all around the capacitor dielectric, and dielectric support structures below the inner conductor. The capacitor is elongated in a length direction parallel to a working surface of the substrate, and the dielectric support structures are spaced along the length direction. The transistor includes a channel structure, a gate structure all around the channel structure, and source/drain (S/D) regions on opposing ends of the channel structure.

Abstract: A semiconductor device includes a stack of dynamic random access memory (DRAM) cell units over a substrate in a vertical direction perpendicular to a working surface of the substrate. At least one DRAM cell unit includes a transistor and a capacitor. The capacitor includes a first metal layer, a capacitor dielectric layer positioned on the first metal layer, and a second metal layer positioned on the capacitor dielectric layer. The capacitor is elongated in a horizontal direction parallel to the working surface of the substrate. The second metal layer has a first end and a second end in the horizontal direction. The transistor includes a channel structure, and a gate structure disposed all around the channel structure. The first metal layer extends in the horizontal direction beyond the first end of the second metal layer to form a drain region and a source region of the transistor.

Abstract: Aspects of the present disclosure provide a semiconductor structure. For example, the semiconductor structure can include a lower transistor including a lower channel that is elongated horizontally; an upper transistor vertically stacked over the lower transistor and including an upper channel that is elongated horizontally; a lower metal capacitor electrically connected to and horizontally elongated from the lower transistor, the lower metal capacitor including a first lower metal plate, a lower dielectric layer that surrounds the first lower metal plate, and a second lower metal plate that surrounds the lower dielectric layer; and an upper metal capacitor vertically stacked over the lower metal capacitor and electrically connected to and horizontally elongated from the upper transistor, the upper metal capacitor including a first upper metal plate, an upper dielectric layer that surrounds the first upper metal plate, and a second upper metal plate that surrounds the upper dielectric layer.

Abstract: Aspects of the present disclosure provide a semiconductor structure. For example, the semiconductor structure can include a lower transistor including a lower channel that is elongated horizontally, and an upper transistor vertically stacked over the lower transistor and including an upper channel that is elongated horizontally. The semiconductor structure can also include a lower metal capacitor electrically connected to and horizontally elongated from the lower transistor. The lower metal capacitor can include a first lower metal plate that is in-plane with the lower channel of the lower transistor. The semiconductor structure can also include an upper metal capacitor vertically stacked over the lower metal capacitor and electrically connected to and horizontally elongated from the upper transistor. The upper metal capacitor can include a first upper metal plate that is in-plane with the upper channel of the upper transistor. method for improving overlay alignment of patterning by correcting wafer shape.

Abstract: Aspects of the present disclosure provide a method for forming a semiconductor structure having separated vertical channel structures. The method can include forming a layer stack on a substrate, the layer stack including alternating metal layers and dielectric layers. The method can further include forming vertically stacked lower and upper vertical channel structures vertically extending through the layer stack, the lower and upper vertical channel structures being separated by a sacrificial layer. The method can further include forming source, drain and gate connections to the lower and upper vertical channel structures, the source, drain and gate connections extending horizontally from the lower and upper vertical channel structures and then vertically to a location above the upper vertical channel structure.

Abstract: Methods for the manufacture of semiconductor devices constructed with three-dimensional (3D) single crystal silicon nano sheets integrated with two-dimensional (2D) materials are disclosed. A device may include a semiconductor material and having a first end and a second end doped with a first polarity; a seed material wrapping around the semiconductor material; a two-dimensional (2D) material around the seed material; an active gate around the 2D material; and a source/drain structure in contact with the first end and the second end of the semiconductor material and in contact with the 2D material, wherein the source/drain structure is doped with a second polarity opposite to the first polarity.

Abstract: One or more 3D VFET structures with 2D material based channels using a wafer transfer technology and a metal first approach are disclosed. Transistor devices can be formed, where each transistor can include an elongate structure extending vertically from a first/source drain contact, a first end of the elongate structure in electrical contact with the first source/drain contact and a second end of the elongate structure in electrical contact with a second source/drain contact. The transistor can also include a channel that includes a 2D material layer extending along an external surface of the elongate structure and a gate structure including a high-k dielectric extending along the 2D material and a gate metal in contact with the high-k dielectric. The 2D material can laterally surround the elongate structure and the gate structure can surround the 2D material.

Abstract: A semiconductor device includes a substrate with a working surface and a transistor formed in the substrate. The transistor includes a complex channel structure which is vertically arranged with respect to the working surface. The complex channel structure includes first and second source-drain (S-D) ends which are provided in a plane extending along the working surface to define an opening to a bounded region of the complex channel structure. The transistor also includes a gate dielectric layer formed on the complex channel structure within the bounded region, and a gate metal layer formed on the gate dielectric layer within the bounded region to form the transistor.

Abstract: One or more 3D transistor structures that use one or more 2D materials as transistor channels along with methods for fabricating the same are disclosed. A 3D transistor can include a source contact, a drain contact, a 2D material forming a channel between the source and drain contacts and surrounding a carrier nanosheet forming a first p-n junction with the source contact and a second p-n junction with the drain contact, and a gate structure comprising a gate dielectric and a gate contact contacting at least a portion of the channel between the first p-n junction and the second p-n junction. The source and drain contacts can comprise a doped semiconductor material and a channel having a first curved profile extending along the source contact and a second curved profile extending along the drain contact.