Patents by Inventor Partha PANDE

Partha PANDE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10103913
    Abstract: In some embodiments, improved routing strategies for small-world network-on-chip (SWNoC) systems are provided. In some embodiments, an ALASH routing strategy or an MROOTS strategy are used in order to improve latency, temperature, and energy use within a network-on-chip system. In some embodiments, millimeter-wave wireless transceivers are used to implement the long-distance links within the small-world network, to create a millimeter-wave small-world network-on-chip (mSWNoC) system. In some embodiments, non-coherent on-off keying (OOK) wireless transceivers are used to implement the wireless links.
    Type: Grant
    Filed: March 25, 2016
    Date of Patent: October 16, 2018
    Assignee: Washington State University
    Inventors: Partha Pande, Deukhyoun Heo
  • Patent number: 9876708
    Abstract: Several embodiments of the present technology are related to network-on-chip based integrated circuits with wireless interconnects. In one embodiment, a computing device includes a plurality of computing cores on a common substrate. The computing cores are organized into a plurality of subnets individually associated with a set of the computing cores, a communications hub associated with the set of the computing cores, and a plurality of conductive or semi-conductive connectors connecting the set of the computing cores into a small world network. The computing device further includes a plurality of wireless transceivers on the substrate, the wireless transceivers being individually associated with one of the communications hubs of a corresponding subnet.
    Type: Grant
    Filed: May 29, 2015
    Date of Patent: January 23, 2018
    Assignee: Washington State University
    Inventor: Partha Pande
  • Patent number: 9608684
    Abstract: Several embodiments of the present technology are related to network-on-chip based integrated circuits, methods of manufacturing or fabricating such integrated circuits, and electronic/computing devices incorporating such integrated circuits. In one embodiment, a computing device includes a substrate, a plurality of computing nodes interconnected by a plurality of interconnects on the substrate to form a wired network. The individual computing nodes include one or more computing processors. The computing device further includes a pair of wireless transceivers individually connected to one of the computing nodes and spaced apart from each other by a network diameter of the wired network.
    Type: Grant
    Filed: February 13, 2014
    Date of Patent: March 28, 2017
    Assignee: Washington State University
    Inventor: Partha Pande
  • Publication number: 20160323127
    Abstract: In some embodiments, improved routing strategies for small-world network-on-chip (SWNoC) systems are provided. In some embodiments, an ALASH routing strategy or an MROOTS strategy are used in order to improve latency, temperature, and energy use within a network-on-chip system. In some embodiments, millimeter-wave wireless transceivers are used to implement the long-distance links within the small-world network, to create a millimeter-wave small-world network-on-chip (mSWNoC) system. In some embodiments, non-coherent on-off keying (OOK) wireless transceivers are used to implement the wireless links.
    Type: Application
    Filed: March 25, 2016
    Publication date: November 3, 2016
    Applicant: Washington State University
    Inventors: Partha Pande, Deukhyoun Heo
  • Publication number: 20160006471
    Abstract: Several embodiments of the present technology are related to network-on-chip based integrated circuits, methods of manufacturing or fabricating such integrated circuits, and electronic/computing devices incorporating such integrated circuits. In one embodiment, a computing device includes a substrate, a plurality of computing nodes interconnected by a plurality of interconnects on the substrate to form a wired network. The individual computing nodes include one or more computing processors. The computing device further includes a pair of wireless transceivers individually connected to one of the computing nodes and spaced apart from each other by a network diameter of the wired network.
    Type: Application
    Filed: February 13, 2014
    Publication date: January 7, 2016
    Inventor: Partha PANDE
  • Publication number: 20150358393
    Abstract: Several embodiments of the present technology are related to network-on-chip based integrated circuits with wireless interconnects. In one embodiment, a computing device includes a plurality of computing cores on a common substrate. The computing cores are organized into a plurality of subnets individually associated with a set of the computing cores, a communications hub associated with the set of the computing cores, and a plurality of conductive or semi-conductive connectors connecting the set of the computing cores into a small world network. The computing device further includes a plurality of wireless transceivers on the substrate, the wireless transceivers being individually associated with one of the communications hubs of a corresponding subnet.
    Type: Application
    Filed: May 29, 2015
    Publication date: December 10, 2015
    Inventor: Partha PANDE