Patents by Inventor Partha Raghavachari

Partha Raghavachari has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5774545
    Abstract: VLSI and ULSI devices like microprocessors and DRAM devices are prone to large scale theft from factories and warehouses. A proposed method of reducing the theft incorporates a small amount of non-volatile flash memory in these devices. The flash memory contains password, device serial number and user identification information. On power-up, the device initiates an encrypted password verification session through a standard interface. If the user supplied password fails, the device's operational ports (any data or control output buses) are tri-stated, thus making the device unusable. The device serial number and user identification information are useful in determining ownership of stolen devices when recovered.
    Type: Grant
    Filed: March 28, 1996
    Date of Patent: June 30, 1998
    Assignee: Lucent Technologies Inc.
    Inventor: Partha Raghavachari
  • Patent number: 5386383
    Abstract: A memory system (30), comprised of a plurality of banks (32.sub.0 -32.sub.7) of DRAM devices (10) is controlled by a memory controller (34) that not only determines the presence and density of the DRAM devices upon power-up, but also controls their addressing during normal operation. The memory controller addresses the DRAM devices in each bank by providing each with a complete row address and a complete column address that simultaneously specifies the row and column address for the condition when the DRAM device is symmetric and asymmetric. In this way, the controller can accommodate both symmetric and asymmetric DRAM devices in the same bank.
    Type: Grant
    Filed: February 28, 1994
    Date of Patent: January 31, 1995
    Assignee: AT&T Corp.
    Inventor: Partha Raghavachari
  • Patent number: 5311520
    Abstract: An electronic circuit (10) for controlling and testing up to eight banks (12) of RAMs (14.sub.1 -14.sub.n) includes a controller portion (20) for controlling accessing of the RAM banks to permit read and write operations to be carried out, and for initiating testing of the RAMs as well. The circuit (10) also includes a data path portion (22) for detecting parity errors in the data written to and read from the RAMs as well as for detecting errors which occur during testing initiated by the control portion. An interface portion (24) may also be provided to allow test commands, status information and error data to be communicated to and from the circuit (10) across a four-wire boundary scan bus.
    Type: Grant
    Filed: August 29, 1991
    Date of Patent: May 10, 1994
    Assignee: AT&T Bell Laboratories
    Inventor: Partha Raghavachari