Patents by Inventor Partha Ranganathan
Partha Ranganathan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8966195Abstract: A system and method is illustrated for identifying an Input/Output (I/O) driver module, using a hypervisor, to receive a read command to read a virtual memory page from a remote memory location. Further, the system and method includes reading the remote virtual memory page, using the I/O driver module, into a memory buffer managed by the I/O driver module. Additionally, the system and method includes storing the virtual memory page in the memory buffer to a persistent storage device. The system and method also includes identifying a remote super page, using a hypervisor, the remote super page including a remote sub page. Additionally, the system and method includes identifying a local super page, using the hypervisor, the local super page including a local sub page. Further, the system and method includes swapping the local sub page for the remote sub page, using the hypervisor, the swapping occurring over a network.Type: GrantFiled: June 26, 2009Date of Patent: February 24, 2015Assignee: Hewlett-Packard Development Company, L.P.Inventors: Jichuan Chang, Kevin Lim, Partha Ranganathan
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Patent number: 8910153Abstract: A system and method is shown that includes an admission control module that resides in a management/driver domain, the admission control module to admit a domain that is part of a plurality of domains, into the computer system based upon one of a plurality of accelerators satisfying a resource request of the domain. The system and method also includes a load balancer module, which resides in the management/driver domain, the load balancer to balance at least one load from the plurality of domains across the plurality of accelerators. Further, the system and method also includes a scheduler module that resides in the management/driver domain, the scheduler to multiplex multiple requests from the plurality of domains to one of the plurality of accelerators.Type: GrantFiled: July 13, 2009Date of Patent: December 9, 2014Assignee: Hewlett-Packard Development Company, L. P.Inventors: Vishakha Gupta, Niraj Tolia, Vanish Talwar, Partha Ranganathan
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Patent number: 8843422Abstract: Illustrated is a system and method for anomaly detection in data centers and across utility clouds using an Entropy-based Anomaly Testing (EbAT), the system and method including normalizing sample data through transforming the sample data into a normalized value that is based, in part, on an identified average value for the sample data. Further, the system and method includes binning the normalized value through transforming the normalized value into a binned value that is based, in part, on a predefined value range for a bin such that a bin value, within the predefined value range, exists for the sample data. Additionally, the system and method includes identifying at least one vector value from the binned value. The system and method also includes generating an entropy time series through transforming the at least one vector value into an entropy value to be displayed as part of a look-back window.Type: GrantFiled: March 31, 2010Date of Patent: September 23, 2014Assignee: Hewlett-Packard Development Company, L.P.Inventors: Chengwei Wang, Vanish Talwar, Partha Ranganathan
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Patent number: 8788739Abstract: A system and method is illustrated for comparing a target memory address and a local memory size using a hypervisor module that resides upon a compute blade, the comparison based upon a unit of digital information for the target memory address and an additional unit of digital information for the local memory size. Additionally, the system and method utilizes swapping of a local virtual memory page with a remote virtual memory page using a swapping module that resides on the hypervisor module, the swapping based upon the comparing of the target memory address and the local memory size. Further, the system and method is implemented to transmit the local virtual memory page to a memory blade using a transmission module that resides upon the compute blade.Type: GrantFiled: June 29, 2009Date of Patent: July 22, 2014Assignee: Hewlett-Packard Development Company, L.P.Inventors: Jichuan Chang, Kevin Lim, Partha Ranganathan
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Patent number: 8645610Abstract: A system and method is illustrated wherein a protocol agent module receives a memory request encoded with a protocol, the memory request identifying an address location in a memory module managed by a buffer. Additionally, the system and method includes a memory controller to process the memory request to identify the buffer that manages the address location in the memory module. Further, the system and method includes an address mapping module to process the memory request to identify at least one super page associated with the memory module, the at least one super page associated with the address location.Type: GrantFiled: June 29, 2009Date of Patent: February 4, 2014Assignee: Hewlett-Packard Development Company, L.P.Inventors: Jichuan Chang, Kevin Lim, Partha Ranganathan
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Patent number: 8638799Abstract: A system and method for implementing a VM to identify a data packet for transmission, the data packet including a QoS the data packet is to receive as compared to another QoS that another data packet is to receive. The system and method further includes a SNIC to pull the data packet from the VM based upon the QoS the data packet is to receive. The system and method may also include a link scheduler module to transmit the data packet based upon the QoS the data packet is to receive. The system and method may also include a receiver to receive a management instruction from a network management device, the management instruction to dictate the QoS the data packet is to receive based upon a SLA.Type: GrantFiled: July 10, 2009Date of Patent: January 28, 2014Assignee: Hewlett-Packard Development Company, L.P.Inventors: Jayaram Mudigonda, Paul T Congdon, Partha Ranganathan
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Patent number: 8392761Abstract: A system and method is shown that includes a processor operatively connected to a memory, the processor to include a memory controller to control access to the memory. The system and method also includes a service processor, co-located on a common board and operatively connected to the processor and the memory, the service processor to include an additional memory controller to control access to the memory as part of a checkpoint regime.Type: GrantFiled: March 31, 2010Date of Patent: March 5, 2013Assignee: Hewlett-Packard Development Company, L.P.Inventors: Matteo Monchiero, Naveen Muralimanohar, Partha Ranganathan
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Publication number: 20120136909Abstract: Illustrated is a system and method for anomaly detection in data centers and across utility clouds using an Entropy-based Anomaly Testing (EbAT), the system and method including normalizing sample data through transforming the sample data into a normalized value that is based, in part, on an identified average value for the sample data. Further, the system and method includes binning the normalized value through transforming the normalized value into a binned value that is based, in part, on a predefined value range for a bin such that a bin value, within the predefined value range, exists for the sample data. Additionally, the system and method includes identifying at least one vector value from the binned value. The system and method also includes generating an entropy time series through transforming the at least one vector value into an entropy value to be displayed as part of a look-back window.Type: ApplicationFiled: March 31, 2010Publication date: May 31, 2012Inventors: Chengwei Wang, Vanish Talwar, Partha Ranganathan
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Publication number: 20120030406Abstract: A system and method is illustrated for comparing a target memory address and a local memory size using a hypervisor module that resides upon a compute blade, the comparison based upon a unit of digital information for the target memory address and an additional unit of digital information for the local memory size. Additionally, the system and method utilizes swapping of a local virtual memory page with a remote virtual memory page using a swapping module that resides on the hypervisor module, the swapping based upon the comparing of the target memory address and the local memory size. Further, the system and method is implemented to transmit the local virtual memory page to a memory blade using a transmission module that resides upon the compute blade.Type: ApplicationFiled: June 29, 2009Publication date: February 2, 2012Inventors: Jichuan Chang, Kevin Lim, Partha Ranganathan
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Publication number: 20120005556Abstract: A system and method is illustrated wherein a protocol agent module receives a memory request encoded with a protocol, the memory request identifying an address location in a memory module managed by a buffer. Additionally, the system and method includes a memory controller to process the memory request to identify the buffer that manages the address location in the memory module. Further, the system and method includes an address mapping module to process the memory request to identify at least one super page associated with the memory module, the at least one super page associated with the address location.Type: ApplicationFiled: June 29, 2009Publication date: January 5, 2012Inventors: Jichuan Chang, Kevin Lim, Partha Ranganathan
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Publication number: 20110246828Abstract: A system and method is shown that includes a processor operatively connected to a memory, the processor to include a memory controller to control access to the memory. The system and method also includes a service processor, co-located on a common board and operatively connected to the processor and the memory, the service processor to include an additional memory controller to control access to the memory as part of a checkpoint regime.Type: ApplicationFiled: March 31, 2010Publication date: October 6, 2011Inventors: Matteo Monchiero, Naveen Muralimanohar, Partha Ranganathan
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Patent number: 7966394Abstract: A system for coordinating information between management entities includes a CIMOM registry broker storing registration information for CIMOMs in the system. The CIMOM registry broker is operable to extract objects from at least some of the CIMOMs in response to a request from an entity external to the system. The CIMOM registry broker is also operable to correlate information in the extracted objects into a single response table, and send the single response table to the entity external to the system. The system also includes a plurality of agents, wherein each agent is associated with one of the CIMOMs and is operable to communicate information from the CIMOMs to the CIMOM registry broker. The system also includes at least one management channel providing bidirectional communication between the CIMOM registry broker and the agents in the system.Type: GrantFiled: October 14, 2008Date of Patent: June 21, 2011Assignee: Hewlett-Packard Development Company, L.P.Inventors: Vanish Talwar, Partha Ranganathan, Jeff Hilland
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Publication number: 20110010721Abstract: A system and method is shown that includes an admission control module that resides in a management/driver domain, the admission control module to admit a domain that is part of a plurality of domains, into the computer system based upon one of a plurality of accelerators satisfying a resource request of the domain. The system and method also includes a load balancer module, which resides in the management/driver domain, the load balancer to balance at least one load from the plurality of domains across the plurality of accelerators. Further, the system and method also includes a scheduler module that resides in the management/driver domain, the scheduler to multiplex multiple requests from the plurality of domains to one of the plurality of accelerators.Type: ApplicationFiled: July 13, 2009Publication date: January 13, 2011Inventors: Vishakha Gupta, Niraj Tolia, Vanish Talwar, Partha Ranganathan
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Publication number: 20110007746Abstract: A system and method for implementing a VM to identify a data packet for transmission, the data packet including a QoS the data packet is to receive as compared to another QoS that another data packet is to receive. The system and method further includes a SNIC to pull the data packet from the VM based upon the QoS the data packet is to receive. The system and method may also include a link scheduler module to transmit the data packet based upon the QoS the data packet is to receive. The system and method may also include a receiver to receive a management instruction from a network management device, the management instruction to dictate the QoS the data packet is to receive based upon a SLA.Type: ApplicationFiled: July 10, 2009Publication date: January 13, 2011Inventors: Jayaram Mudigonda, Paul T. Congdon, Partha Ranganathan
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Publication number: 20100332720Abstract: A system and method is illustrated for identifying an Input/Output (I/O) driver module, using a hypervisor, to receive a read command to read a virtual memory page from a remote memory location. Further, the system and method includes reading the remote virtual memory page, using the I/O driver module, into a memory buffer managed by the I/O driver module. Additionally, the system and method includes storing the virtual memory page in the memory buffer to a persistent storage device. The system and method also includes identifying a remote super page, using a hypervisor, the remote super page including a remote sub page. Additionally, the system and method includes identifying a local super page, using the hypervisor, the local super page including a local sub page. Further, the system and method includes swapping the local sub page for the remote sub page, using the hypervisor, the swapping occurring over a network.Type: ApplicationFiled: June 26, 2009Publication date: December 30, 2010Inventors: Jichuan Chang, Kevin Lim, Partha Ranganathan
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Publication number: 20090271646Abstract: A multi-core system including cores and voltage sources supplying power to the cores. The cores are divided into clusters based on the particular voltage source supplying power to each core. Power management is performed in the multi-core system based on one or more of core utilization and a management policy.Type: ApplicationFiled: October 31, 2008Publication date: October 29, 2009Inventors: Vanish Talwar, Partha Ranganathan, Sanjay Kumar