Abstract: Disclosed are systems, devices and methods for a quantitative aptamer-based viral assay. In some aspects, an aptamer-based viral assay device includes a substrate and a biochemical complex conjugated to the substrate, which comprises an aptamer that is initially bound to an enzyme-tagged complementary strand of nucleotides, the aptamer corresponding to an antigen of a virus (e.g., SARS-CoV-2) that has a higher binding affinity to the aptamer than the complementary strand of nucleotides, wherein, when the device is exposed to a solution containing the virus, the enzyme-tagged strand is released from the aptamer as the aptamer binds the antigen of the virus, such that the released enzyme is capable of converting a substance to an analyte that is measurable by a remote analyte meter to correlate with a parameter of the virus in the solution.

Abstract: Provided herein are methods for determining a diagnosis and/or prognosis for prostate cancer using the ratio of FOXC1:FOXA1 in a sample obtained from a subject.

Abstract: Various embodiments of the present technology generally relate to file sharing, encryption, and protection of digital assets. More specifically, some embodiments of the present technology relate to computer files comprising an unencrypted file combined with an encrypted file, and methods for creation of such combined files. The unencrypted file can be read by target applications and can present a variety of information (e.g., contact information, registration information, etc.). The encrypted data may be accessed only when the proper management software, drivers, application programming interfaces, and other components of a runtime environment have been installed on a computing device.

Abstract: Various embodiments of the present technology generally relate to file sharing, encryption, and protection of digital assets. More specifically, some embodiments of the present technology relate to computer files comprising an unencrypted file combined with an encrypted file, and methods for creation of such combined files. The unencrypted file can be read by target applications and can present a variety of information (e.g., contact information, registration information, etc.). The encrypted data may be accessed only when the proper management software, drivers, application programming interfaces, and other components of a runtime environment have been installed on a computing device.

Abstract: Provided herein are methods for determining a diagnosis and/or prognosis for prostate cancer using the ratio of FOXC1:FOXA1 in a sample obtained from a subject.

Abstract: Various embodiments of the present technology generally relate to file sharing, encryption, and protection of digital assets. More specifically, some embodiments of the present technology relate to computer files comprising an unencrypted file combined with an encrypted file, and methods for creation of such combined files. The unencrypted file can be read by target applications and can present a variety of information (e.g., contact information, registration information, etc.). The encrypted data may be accessed only when the proper management software, drivers, application programming interfaces, and other components of a runtime environment have been installed on a computing device.

Abstract: Provided herein are methods for determining a diagnosis and/or prognosis for prostate cancer using the ratio of FOXC1:FOXA1 in a sample obtained from a subject.

Abstract: In one embodiment, a method of theranostic classification of a breast cancer tumor is provided, comprising obtaining a breast cancer tumor sample from a subject, detecting an expression level of FOXC1, comparing the expression level of FOXC1 to a predetermined cutoff level, and classifying the breast cancer tumor sample as belonging to a theranostic basal-like breast cancer tumor subtype or a theranostic hybrid basal-like breast cancer tumor subtype when the expression level of FOXC1 is higher than the predetermined cutoff level.

Abstract: An analyte sensor and systems for determining analyte levels in a user's body. The analyte sensor and systems are adapted to be used with single dose medication devices and include a communication system to transmit the communications from the analyte sensor to the user to notify the user of an estimated amount of fluid to deliver to the user's body. More particularly, these apparatuses and methods for use are for providing convenient monitoring of blood glucose levels in determining the appropriate amount of insulin to deliver.

Abstract: A method is provided that finds the largest ‘k’ difference values in decreasing order from a list of ‘n’ arbitrary numbers. The method uses the property of sorted numbers to organize the list of all the differences in a way that reduces the size of the solution space. The time complexity of the solution space using the method is O(k2), as compared to O(n2) in the conventional exhaustive method. The overall time complexity of the method is bound by the complexity of the algorithm used to sort the input list of numbers. The memory complexity of the method is less than the exhaustive method when k<<n.

Abstract: The state nodes in a sequential digital circuit are identified by identifying the minimal combinatorial feedback loops that are present in the digital circuit. Each minimal combinatorial feedback loop has at least one driver node, and one driver node from each minimal combinatorial feedback loop is assigned to be the state node for the loop.

Abstract: A method is provided for simulating a sequential digital circuit module given a set of input conditions and a current state for the circuit. The method comprises initiating all state nodes of the circuit module to logic values stored in the current state, initializing all sequential submodules of the circuit module to the states stored in the current state, simulating the circuit module after initialization, and after completion of the simulation step, reporting the output logic values and associated delays and storing the logic values of the state nodes and the states of the sequential modules in the next state in the circuit module, multiple value changes in the state nodes of the circuit module being recorded on the next state.

Abstract: An integrated circuit design simulation method is provided that takes advantage of the fact that, when an instance of a circuit module has been simulated under a given set of input conditions, and the resulting output values and delays have been evaluated, another instance of the same module need not be re-simulated when it has the same input combination as the prior circuit module instance. The results computed earlier for the earlier circuit module instance can be re-used for the current circuit module instance.

Abstract: Built-In Self Test (BIST) is a test technique wherein semiconductor integrated circuit devices test themselves during their operation lifetime. BIST techniques do not necessarily require additional hardware; they can be implemented using dedicated software routines. Various BIST algorithms and techniques have been proposed for testing random access memory (RAM) devices. The present invention provides an architecture for the memory-test interface that allows the serial transfer of the test background data from the BIST controller to the interface of the memory-under-test using a single bit with serial-to-parallel data conversion using a shift register in the memory interface. The size of the shift register is equal to the word width of the memory-under-test.

Abstract: Sequential digital integrated circuits have stable state nodes that are capable of retaining their state (logic value) even in the absence of any input directly driving these points. However, in addition to stable state nodes, some custom-designed digital circuits have so-called transient state nodes. A transient state node is defined as node that can directly affect the value of a stable state node and is combinatorially driven by inputs of the circuit, but the transition delay from at least one input to the node is greater than a predefined threshold value. Identifying such transient state nodes, along with the stable state nodes, is critical for the efficient simulation of custom digital circuits by a hierarchical device level digital simulator. A method is provided herein for identifying transient state nodes in a digital circuit, given the circuit's netlist and the identity of the stable state nodes in the circuit.

Abstract: An analyte sensor and systems for determining analyte levels in a user's body. The analyte sensor and systems are adapted to be used with single dose medication devices and include a communication system to transmit the communications from the analyte sensor to the user to notify the user of an estimated amount of fluid to deliver to the user's body. More particularly, these apparatuses and methods for use are for providing convenient monitoring of blood glucose levels in determining the appropriate amount of insulin to deliver.

Abstract: A method for device level simulation of a circuit modeled by a set of CCR graphs, a computer system programmed to perform such a method, and a computer readable medium which stores code for implementing such a method. Typically, the circuit includes MOS transistors having unknown gate potentials, each CCR graph includes a top rail, and a bottom rail, and variable nodes, each of the transistors having unknown gate potential is modeled in the CCR graphs as a selectable resistor having a selected one of a first resistance and a much larger second resistance, and the method includes the steps of determining potentials at variable nodes of one of the CCR graphs with each selectable resistor of the graph having its first resistance (and also with each selectable resistor of the graph having its second resistance) without determining effective resistances between the variable nodes of the graph and the top rail or bottom rail.

Abstract: The quality assurance of all released runset files should ideally be 100% complete to ensure the best quality of the runsets. This means that the designs used for testing should be sufficient to test all of the design rules with the appropriate data in the runset to reach 100% coverage, which is not easy to ensure. The present invention provides a methodology that addresses this problem by quantitatively measuring the test coverage of backend verification runsets. The methodology not only reports the uncovered rules, but also assists the quality assurance engineers in locating reasons as to why those rules are not covered and how coverage can be improved by designing appropriate test cases.

Abstract: State nodes in a sequential digital circuit are identified using a graph-based method based upon the topology of the circuit. In accordance with the method, the device level circuit netlist is reduced to a graph representation using a well-defined set of rules. The unique properties of state nodes can be translated to properties of the graph representation of the circuit. Identification of state nodes is required for proper initialization of sequential circuits for simulation by a device level digital simulator.

Abstract: The state nodes in a sequential digital circuit are identified by identifying the minimal combinatorial feedback loops that are present in the digital circuit. Each minimal combinatorial feedback loop has at least one driver node, and one driver node from each minimal combinatorial feedback loop is assigned to be the state node for the loop.