Abstract: A bitstream modifier is operative on a packet which uses repetition coding. The bitstream modifier increases randomness of the data in a deterministic manner such that spectral spurs from repetition coding are greatly reduced, thereby providing greater available transmit power. In another example of the invention, baseband samples of a header and/or payload for a Bluetooth packet are modified by a canonical sequence with a low slew rate for data such that the variations in frequency may be tracked by a receiver and the transmitted spectral spurs reduced.

Abstract: The present invention is an controller for dynamically allocating RAM between powersave code copied from ROM and transient RAM memory used for storing packets. When the utilization of the transient RAM memory is low, code segments are copied from ROM and executed from RAM using a RAM pointer table which is updated after the code segments are copied over from ROM, and when the utilization of the transient RAM memory is high, code segments are deallocated from RAM and the pointer table is updated to point to the corresponding location in flash ROM.

Abstract: An automatic artwork review system validates an artwork or a product label based on a received label specification document. Text extracted from the product label is chunked into sentences and words. Character-wise comparison is executed to identify the best match text from the label specification document for the sentence chunks from the product label. If the corresponding best match texts bears a similarity higher than a predetermined threshold to selected text including one or more sentence chunks, no errors are raised. If the similarity of the best match text to the selected text is not higher than the predetermined threshold, the specific errors occurring in the selected text and the particular portions where such errors are present are identified. The information regarding the errors can be output via one or more of an output user interface or a label compliance report.

Abstract: A multi-thread processor has a canonical thread map register which outputs a sequence of thread_id values indicating a current thread for execution. The thread map register is programmable to provide granularity of number of cycles of the canonical sequence assigned to each thread. In one example of the invention, the thread map register has repeating thread identifiers in a sequential or non-sequential manner to overcome memory latency and avoid thread stalls. In another example of the invention, separate interrupt tasks are placed on each thread to reduce interrupt processing latency.

Abstract: A communications processor is operative in a plurality of modes including at least a high performance mode, a power savings mode with lower computational capability, and a shutdown mode with a wakeup capability. A memory for the communications processor has a high speed segment and a low speed segment, the high speed segment and low speed segment respectively on a high speed data bus and a low speed data bus, the high speed data bus and low speed data bus coupled by a bidirectional bridge.

Abstract: A mesh receiver has a wakeup receiver for reception of a wakeup sequence formed by keyed RF or a sequence of wireless packets and gaps, a transmitter forming low speed RF wakeup sequence to other mesh stations, a mesh receiver for reception of high speed WLAN packets, the transmitter sending a wireless ACK packet in response to a wakeup sequence, the mesh receiver thereafter receiving wireless packets from a remote station, the mesh transmitter sending an ACK, the mesh station thereafter identifying a next hop station, and sending a wakeup sequence to that station, after receipt of an ACK, sending the data, the mesh receiver and mesh transmitter thereafter going to sleep.

Abstract: A mesh receiver has a wakeup receiver for reception of a wakeup sequence formed by keyed RF or a sequence of wireless packets and gaps, a transmitter forming low speed RF wakeup sequence to other mesh stations, a mesh receiver for reception of high speed WLAN packets, the transmitter sending a wireless ACK packet in response to a wakeup sequence, the mesh receiver thereafter receiving wireless packets from a remote station, the mesh transmitter sending an ACK, the mesh station thereafter identifying a next hop station, and sending a wakeup sequence to that station, after receipt of an ACK, sending the data, the mesh receiver and mesh transmitter thereafter going to sleep.

Abstract: An automatic artwork review system validates an artwork or a product label based on a received label specification document. Text extracted from the product label is chunked into sentences and words. Character-wise comparison is executed to identify the best match text from the label specification document for the sentence chunks from the product label. If the corresponding best match texts bears a similarity higher than a predetermined threshold to selected text including one or more sentence chunks, no errors are raised. If the similarity of the best match text to the selected text is not higher than the predetermined threshold, the specific errors occurring in the selected text and the particular portions where such errors are present are identified. The information regarding the errors can be output via one or more of an output user interface or a label compliance report.

Abstract: A task processor has a low power connectivity processor and a high performance applications processor. Software processes have a component operative on a connectivity processor and a component operative on an applications processor. The low power connectivity processor is coupled to a low power front end for wireless packets and the high performance applications processor is coupled to a high performance front end. A power controller is coupled to the low power front end and enables the applications processor and high performance front end when wireless packets which require greater processing capacity are received, and removes power from the applications processor and high performance front end at other times.

Abstract: SCAN operations for databases where scan time is dependent on a payload size consume too much memory space and computing time as payload sizes increase. A database table is configured to include an additional index mapping column that stores bitmaps related to the corresponding row of the table. Each bit in the bitmap corresponds to a column and indicates whether that column stores a value. Inclusion of an index column in a table decouples the time it takes to perform the SCAN operation on a column from the payload size of data stored in the column. The bitmaps stored in the index column are relatively small and uniform in size, so the SCAN operation on such a database requires only for the bitmap values of the applicable rows to be obtained from the index column and inspected.

Abstract: SCAN operations for databases where scan time is dependent on a payload size consume too much memory space and computing time as payload sizes increase. A database table is configured to include an additional index mapping column that stores bitmaps related to the corresponding row of the table. Each bit in the bitmap corresponds to a column and indicates whether that column stores a value. Inclusion of an index column in a table decouples the time it takes to perform the SCAN operation on a column from the payload size of data stored in the column. The bitmaps stored in the index column are relatively small and uniform in size, so the SCAN operation on such a database requires only for the bitmap values of the applicable rows to be obtained from the index column and inspected.

Abstract: The present invention is an controller for dynamically allocating RAM between powersave code copied from ROM and transient RAM memory used for storing packets. When the utilization of the transient RAM memory is low, code segments are copied from ROM and executed from RAM using a RAM pointer table which is updated after the code segments are copied over from ROM, and when the utilization of the transient RAM memory is high, code segments are deallocated from RAM and the pointer table is updated to point to the corresponding location in flash ROM.

Abstract: A mesh receiver has a wakeup receiver for reception of a wakeup sequence formed by keyed RF or a sequence of wireless packets and gaps, a transmitter forming low speed RF wakeup sequence to other mesh stations, a mesh receiver for reception of high speed WLAN packets, the transmitter sending a wireless ACK packet in response to a wakeup sequence, the mesh receiver thereafter receiving wireless packets from a remote station, the mesh transmitter sending an ACK, the mesh station thereafter identifying a next hop station, and sending a wakeup sequence to that station, after receipt of an ACK, sending the data, the mesh receiver and mesh transmitter thereafter going to sleep.

Abstract: A multi-thread processor has a canonical thread map register which outputs a sequence of thread_id values indicating a current thread for execution. The thread map register is programmable to provide granularity of number of cycles of the canonical sequence assigned to each thread. In one example of the invention, the thread map register has repeating thread identifiers in a sequential or non-sequential manner to overcome memory latency and avoid thread stalls. In another example of the invention, separate interrupt tasks are placed on each thread to reduce interrupt processing latency.

Abstract: The present invention is an controller for dynamically allocating RAM between powersave code copied from ROM and transient RAM memory used for storing packets. When the utilization of the transient RAM memory is low, code segments are copied from ROM and executed from RAM using a RAM pointer table which is updated after the code segments are copied over from ROM, and when the utilization of the transient RAM memory is high, code segments are deallocated from RAM and the pointer table is updated to point to the corresponding location in flash ROM.

Abstract: A mesh receiver has a wakeup receiver for reception of a wakeup sequence formed by keyed RF or a sequence of wireless packets and gaps, a transmitter forming low speed RF wakeup sequence to other mesh stations, a mesh receiver for reception of high speed WLAN packets, the transmitter sending a wireless ACK packet in response to a wakeup sequence, the mesh receiver thereafter receiving wireless packets from a remote station, the mesh transmitter sending an ACK, the mesh station thereafter identifying a next hop station, and sending a wakeup sequence to that station, after receipt of an ACK, sending the data, the mesh receiver and mesh transmitter thereafter going to sleep.

Abstract: A multi-thread processor has a canonical thread map register which outputs a sequence of thread_id values indicating a current thread for execution. The thread map register is programmable to provide granularity of number of cycles of the canonical sequence assigned to each thread. In one example of the invention, the thread map register has repeating thread identifiers in a sequential or non-sequential manner to overcome memory latency and avoid thread stalls. In another example of the invention, separate interrupt tasks are placed on each thread to reduce interrupt processing latency.

Abstract: A communications processor is operative in a plurality of modes including at least a high performance mode, a power savings mode with lower computational capability, and a shutdown mode with a wakeup capability. A memory for the communications processor has a high speed segment and a low speed segment, the high speed segment and low speed segment respectively on a high speed data bus and a low speed data bus, the high speed data bus and low speed data bus coupled by a bidirectional bridge.