Abstract: A wireless signal processor includes an analog front end for generating at least one baseband analog signal, at least one analog to digital converter for converting the baseband signal into a digital signal, the analog to digital converter having a resolution width and a sampling rate, and a baseband processor for measuring the signal energy in the analog to digital converter output, and when the incoming signal energy level increases or a baseband processor detects a packet, at least one of the sampling rate or resolution width also increases until the end of the packet, after which the sample rate and resolution are reduced to an interpacket rate and resolution. Additionally, the sampling rate and resolution increase after packet detection at rates and resolutions which are dependent on packet type and data rate.

Abstract: A wireless signal processor for use in identifying a maximum Carrier to Noise Interference Ratio (CINR) associated with a plurality of received OFDMA subcarriers has a candidate generator for forming a plurality of candidate values from a particular set of received subcarriers by forming candidate values based on the received subcarriers in combination with possible integer preamble offsets and possible preamble values. A candidate evaluator selects which of the possible preamble values and integer frequency offset values have the maximum CINR, and provides the maximum CINR with IFO and preamble index as outputs.

Abstract: A wireless signal processor for use in identifying a maximum Carrier to Noise Interference Ratio (CINR) associated with a plurality of received OFDMA subcarriers has a candidate generator for forming a plurality of candidate values from a particular set of received subcarriers by forming candidate values based on the received subcarriers in combination with possible integer preamble offsets and possible preamble values. A candidate evaluator selects which of the possible preamble values and integer frequency offset values have the maximum CINR, and provides the maximum CINR with IFO and preamble index as outputs.

Abstract: A SINR estimator receiving a symbol stream has a delay element coupled to the symbol stream to produce a delayed symbol stream, which is also coupled to a conjugator. A first multiplier forms a product from the symbol stream and the output of the conjugator, thereafter summing these values over an interval L and scaling by L to form a correlated power estimate Cn. A second multiplier forms a product from the symbol stream which is multiplied by the conjugate of the input, thereafter summing these values over the preamble interval 2L and scaling by 2L to form a non-correlated power estimate Pn. Cn and Pn are compared to generate an SINR estimate.

Abstract: During the preamble interval of a wireless packet, a receiver estimates the SINR of the preamble, and also examines the packet header to determine the data rate, length, and destination address. If the SINR as determined from the preamble is below a threshold, or if the SINR combined with the data rate from the packet header is below a threshold, the receiver is powered down for the duration of the current packet. Additionally, if the packet header bears a destination address for a different station from the one receiving it, the receiver is powered down for the duration of the packet. In this manner, the receiver power is only used to receive packets that have sufficient SINR to be correctly received for their data rate, or are destined for the present station. The reduction in power consumption results in longer battery life for the station.

Abstract: An OFDM symbol comprises information subcarriers which carry the information to be transmitted, accompanied by edge subcarriers, which are selected to minimize the PAPR of the transmitted signal. The selection of edge subcarriers which minimizes PAPR enables either higher power transmission for the same information content, or lower power consumption for the same transmitted symbol power.

Abstract: An RF receiver which produces quadrature digitized outputs and has a gain control is coupled to a digital gain controller which converts the quadrature digitized outputs into an rms voltage, and iterates over a finite number of steps to quickly control the gain to a level sufficient to achieve subsequent digital signal processing without limitations caused by insufficient dynamic range or nonlinear saturation effects caused by insufficient signal or excessive signal at the A/D input, respectively.

Abstract: A quantizer has a plurality of decision blocks, each coupled from input to output, where each decision blocks output generates a binary value that is an unchanged decision block input if the decision block input is below the threshold input level divided by a power of 2, or the decision block subtracts a threshold divided by the power of 2 and passes this result as the decision block output. The quantizer output is formed from the bits of each comparison from each decision block. The threshold is developed from a channel noise variance which may be multiplied by a scale factor related to coding type and rate. In this manner, a large number of input bits to be quantized may be converted to a smaller number of quantizer output bits, while preserving the dynamic range information required to correctly decode signals passed through a communications channel having multi-path frequency selective fading.