Abstract: Embodiments provide systems and methods for generating application binaries having self-triage repair capabilities. For example, embodiments enable an independent software vendor (ISV) to statically compile application source code into a self-triaging application binary (STAB) having a release-time executable. Should the release-time executable generate runtime errors when executed, the STAB can apply one or more triage approaches to itself to morph into a triaged executable that executes without some or all of the compiler optimizations that resulted in the errors (e.g., and without generating those errors on subsequent execution).

Abstract: Methods, apparatuses, and systems that allow a microprocessor to optimally select an assist unit (co-processor) to reduce completion times for completing processing requests to execute functions. The methods, apparatuses, and systems include assist unit hardware, assist unit management software, or a combination of the two to optimally select the assist unit for completing a specific processing request. In optimally selecting an assist unit, the methods, apparatuses, and systems calculate estimated times for completing the processing request with conventional means and with assist units. The times are then compared to determine the fastest time for completing a specific processing request.

Abstract: Methods are disclosed of compiling a software application having multiple functions. At least one of the functions is identified as a targeted function having a significant contribution to performance of the software application. A code version of the targeted function is generated with one of multiple machine models corresponding to different target utilizations for a target architecture, specifically corresponding to the one with the greatest of the different target utilizations. The generated code version of the targeted function is matched with an application thread of the target architecture.

Abstract: Embodiments of the invention provide systems and methods for automatically and adaptively optimizing compilation of application code using a rule-based optimization analyzer (RUBOA) that can command a compiler to apply and adapt optimizations at the code segment level according to gathered performance data. For example, source code can be canonically compiled, and annotations can associate compiled code sections with source code sections. The generated binary can then be executed and monitored to gather performance characteristics. The RUBOA can apply the gathered performance characteristics and annotations to a pre-defined rule set to generate compiler optimizations, each associated with and parametrically tailored to respective source code segments.

Abstract: Embodiments of the invention provide systems and methods for automatically and adaptively optimizing compilation of application code using a rule-based optimization analyzer (RUBOA) that can command a compiler to apply and adapt optimizations at the code segment level according to gathered performance data. For example, source code can be canonically compiled, and annotations can associate compiled code sections with source code sections. The generated binary can then be executed and monitored to gather performance characteristics. The RUBOA can apply the gathered performance characteristics and annotations to a pre-defined rule set to generate compiler optimizations, each associated with and parametrically tailored to respective source code segments.

Abstract: Methods, apparatuses, and systems that allow a microprocessor to optimally select an assist unit (co-processor) to reduce completion times for completing processing requests to execute functions. The methods, apparatuses, and systems include assist unit hardware, assist unit management software, or a combination of the two to optimally select the assist unit for completing a specific processing request. In optimally selecting an assist unit, the methods, apparatuses, and systems calculate estimated times for completing the processing request with conventional means and with assist units. The times are then compared to determine the fastest time for completing a specific processing request.

Abstract: Embodiments include systems and methods for reducing instruction cache miss penalties during application execution. Application code is profiled to determine “hot” code regions likely to experience instruction cache miss penalties. The application code can be linearized into a set of traces that include the hot code regions. Embodiments traverse the traces in reverse, keeping track of instruction scheduling information, to determine where an accumulated instruction latency covered by the code blocks exceeds an amount of latency that can be covered by prefetching. Each time the accumulated latency exceeds the amount of latency that can be covered by prefetching, a prefetch instruction can be scheduled in the application code. Some embodiments insert additional prefetches, merge prefetches, and/or adjust placement of prefetches to account for scenarios, such as loops, merging or forking branches, edge confidence values, etc.

Abstract: Methods are disclosed of compiling a software application having multiple functions. At least one of the functions is identified as a targeted function having a significant contribution to performance of the software application. A code version of the targeted function is generated with one of multiple machine models corresponding to different target utilizations for a target architecture, specifically corresponding to the one with the greatest of the different target utilizations. The generated code version of the targeted function is matched with an application thread of the target architecture.

Abstract: Methods are disclosed of compiling a software application having multiple functions. At least one of the functions is identified as a targeted function having a significant contribution to performance of the software application. A code version of the targeted function is generated with one of multiple machine models corresponding to different target utilizations for a target architecture, specifically corresponding to the one with the greatest of the different target utilizations. The generated code version of the targeted function is matched with an application thread of the target architecture.

Abstract: Embodiments include systems and methods for reducing instruction cache miss penalties during application execution. Application code is profiled to determine “hot” code regions likely to experience instruction cache miss penalties. The application code can be linearized into a set of traces that include the hot code regions. Embodiments traverse the traces in reverse, keeping track of instruction scheduling information, to determine where an accumulated instruction latency covered by the code blocks exceeds an amount of latency that can be covered by prefetching. Each time the accumulated latency exceeds the amount of latency that can be covered by prefetching, a prefetch instruction can be scheduled in the application code. Some embodiments insert additional prefetches, merge prefetches, and/or adjust placement of prefetches to account for scenarios, such as loops, merging or forking branches, edge confidence values, etc.

Abstract: Embodiments of the invention provide systems and methods for throughput-aware software pipelining in compilers to produce optimal code for single-thread and multi-thread execution on multi-threaded systems. A loop is identified within source code as a candidate for software pipelining. An attempt is made to generate pipelined code (e.g., generate an instruction schedule and a set of register assignments) for the loop in satisfaction of throughput-aware pipelining criteria, like maximum register count, minimum trip count, target core pipeline resource utilization, maximum code size, etc. If the attempt fails to generate code in satisfaction of the criteria, embodiments adjust one or more settings (e.g., by reducing scalarity or latency settings being used to generate the instruction schedule).

Abstract: Methods are disclosed of compiling a software application having multiple functions. At least one of the functions is identified as a targeted function having a significant contribution to performance of the software application. A code version of the targeted function is generated with one of multiple machine models corresponding to different target utilizations for a target architecture, specifically corresponding to the one with the greatest of the different target utilizations. The generated code version of the targeted function is matched with an application thread of the target architecture.

Abstract: Embodiments of the invention provide systems and methods for throughput-aware software pipelining in compilers to produce optimal code for single-thread and multi-thread execution on multi-threaded systems. A loop is identified within source code as a candidate for software pipelining. An attempt is made to generate pipelined code (e.g., generate an instruction schedule and a set of register assignments) for the loop in satisfaction of throughput-aware pipelining criteria, like maximum register count, minimum trip count, target core pipeline resource utilization, maximum code size, etc. If the attempt fails to generate code in satisfaction of the criteria, embodiments adjust one or more settings (e.g., by reducing scalarity or latency settings being used to generate the instruction schedule).

Abstract: One embodiment of the present invention provides a system that generates code for software scouting the regions of a program. During operation, the system receives source code for a program. The system then compiles the source code. In the first step of the compilation process, the system identifies a first set of loops from a hierarchy of loops in the source code, wherein each loop in the first set of loops contains at least one effective prefetch candidate. Then, from the first set of loops, the system identifies a second set of loops where scout-mode prefetching is profitable. Next, for each loop in the second set of loops, the system produces executable code for a helper-thread which contains a prefetch instruction for each effective prefetch candidate. At runtime the helper-thread is executed in parallel with the main thread in advance of where the main thread is executing to prefetch data items for the main thread.

Abstract: One embodiment of the present invention provides a system for communicating and performing synchronization operations between a main thread and a helper-thread. The system starts by executing a program in a main thread. Upon encountering a loop which has associated helper-thread code, the system commences the execution of the code by the helper-thread separately and in parallel with the main thread. While executing the code by the helper-thread, the system periodically checks the progress of the main thread and deactivates the helper-thread if the code being executed by the helper-thread is no longer performing useful work. Hence, the helper-thread is executes in advance of where the main thread is executing to prefetch data items for the main thread without unnecessarily consuming processor resources or hampering the execution of the main thread.