Abstract: A memory device includes a command interface that when operating receives a write command, an input output interface that when in operation receives data signals in conjunction with the write command, and error detection circuitry coupled to the input output interface. The error detection circuitry is configured to generate a first signal indicative of a first period of time during which a first determination is made regarding a first portion of the data signals utilizing a first data strobe signal as a first clock signal, generate a second signal indicative of a second period of time during which a second determination is made regarding a second portion of the data signals utilizing a second data strobe signal as a second clock signal, and generate a control signal based upon the first signal, the second signal, and a slower of the first data strobe signal and the second data strobe signal.

Abstract: Disclosed are methods for reading data from a storage buffer. One such method may include retrieving a first set of data during a first period of time. The method may also include delaying data retrieval during a second period of time after the first period of time. The method may include outputting at least a portion of the first set of data during the first period of time and the second period of time. The first period of time is substantially similar to the second period of time.

Abstract: Systems and methods for injecting a toggling signal in a command pipeline configured to receive a multiple command types for the memory device. Toggling circuitry is configured to inject the toggling signal into at least a portion of the command pipeline when the memory device is in a power saving mode and the command pipeline is clear of valid commands. The toggling is blocked from causing writes by disabling a data strobe when a command that is invalid in the power saving mode is asserted during the power saving mode.

Abstract: Systems and methods for injecting a toggling signal in a command pipeline configured to receive a multiple command types for the memory device. Toggling circuitry is configured to inject the toggling signal into at least a portion of the command pipeline when the memory device is in a power saving mode and the command pipeline is clear of valid commands. The toggling is blocked from causing writes by disabling a data strobe when a command that is invalid in the power saving mode is asserted during the power saving mode.

Abstract: Disclosed are methods for reading data from a storage buffer. One such method may include retrieving a first set of data during a first period of time. The method may also include delaying data retrieval during a second period of time after the first period of time. The method may include outputting at least a portion of the first set of data during the first period of time and the second period of time. The first period of time is substantially similar to the second period of time.

Abstract: A multi-phase clock generator has a set of transistors, a first latch, and a second latch. The set of transistors may be arranged in a sense amplifier latch architecture, in which the set of transistors include a first inverter and a second inverter. The first inverter may provide a first phase data strobe signal and the second inverter may provide a second phase data strobe signal. The first latch and the second latch are coupled to the set of transistors. The set of transistors may receive a first portion of current at the first inverter and a second portion of current at the second inverter. The set of transistors may amplify the first portion of current in response to the first portion being greater than the second portion. The set of transistors may also drive the first phase data strobe signal using the amplified first portion.

Abstract: A multi-phase clock generator has a set of transistors, a first latch, and a second latch. The set of transistors may be arranged in a sense amplifier latch architecture, in which the set of transistors include a first inverter and a second inverter. The first inverter may provide a first phase data strobe signal and the second inverter may provide a second phase data strobe signal. The first latch and the second latch are coupled to the set of transistors. The set of transistors may receive a first portion of current at the first inverter and a second portion of current at the second inverter. The set of transistors may amplify the first portion of current in response to the first portion being greater than the second portion. The set of transistors may also drive the first phase data strobe signal using the amplified first portion.

Abstract: The systems and methods provided herein relate to a command interface/memory device that supports multiple modes of command acquisition. A current command acquisition mode from a set of supported command acquisition modes that each define a corresponding command execution frequency is identified. Based upon the identified mode, clock cycles that will be used to acquire portions of a command address from are identified. The portions of the command address are acquired from the identified clock cycles and a command based upon the acquired portions of the command address is executed.

Abstract: A semiconductor device includes a clock gating tree comprising a first clock gating stage and a second clock gating stage. The first clock gating stage is configured to receive an activate detection signal and to activate clocking events in the second clock gating stage in response to the activate detection signal. The clocking events are not activated in the absence of the activate detection signal.

Abstract: The systems and methods provided herein relate to a command interface/memory device that supports multiple modes of command acquisition. A current command acquisition mode from a set of supported command acquisition modes that each define a corresponding command execution frequency is identified. Based upon the identified mode, clock cycles that will be used to acquire portions of a command address from are identified. The portions of the command address are acquired from the identified clock cycles and a command based upon the acquired portions of the command address is executed.

Abstract: The systems and methods provided herein acquire a command over multiple clock cycles and fires it. When a chip select signal (CS) transitions, a first portion of a command address is captured in a first clock cycle after the CS transitions. Then, a second portion of the command address is captured in a second clock cycle immediately after the first clock cycle or in a third clock cycle immediately following the second clock cycle. An internal command is fired, using the first portion of the command address and the second portion of the command address.

Abstract: A semiconductor device includes a clock gating tree comprising a first clock gating stage and a second clock gating stage. The first clock gating stage is configured to receive an activate detection signal and to activate clocking events in the second clock gating stage in response to the activate detection signal. The clocking events are not activated in the absence of the activate detection signal.

Abstract: A semiconductor device includes a clock gating tree comprising a first clock gating stage and a second clock gating stage. The first clock gating stage is configured to receive an activate detection signal and to activate clocking events in the second clock gating stage in response to the activate detection signal. The clocking events are not activated in the absence of the activate detection signal.

Abstract: A semiconductor device includes a first functional block. The first functional block includes one or more input buffers configured to receive signals, and one or more flip-flops configured to receive the signals from the one or more input buffers and output the received signals from the first functional block. The semiconductor device also includes a second functional block coupled to the first functional block. The second functional block includes a decode logic configured to directly receive the output signals from the one or more flip-flops of the first functional block.

Abstract: The systems and methods provided herein acquire a command over multiple clock cycles and fires it. When a chip select signal (CS) transitions, a first portion of a command address is captured in a first clock cycle after the CS transitions. Then, a second portion of the command address is captured in a second clock cycle immediately after the first clock cycle or in a third clock cycle immediately following the second clock cycle. An internal command is fired, using the first portion of the command address and the second portion of the command address.

Abstract: A semiconductor device includes a first functional block. The first functional block includes one or more input buffers configured to receive signals, and one or more flip-flops configured to receive the signals from the one or more input buffers and output the received signals from the first functional block. The semiconductor device also includes a second functional block coupled to the first functional block. The second functional block includes a decode logic configured to directly receive the output signals from the one or more flip-flops of the first functional block.

Abstract: A semiconductor device includes a clock gating tree comprising a first clock gating stage and a second clock gating stage. The first clock gating stage is configured to receive an activate detection signal and to activate clocking events in the second clock gating stage in response to the activate detection signal. The clocking events are not activated in the absence of the activate detection signal.

Abstract: The systems and methods provided herein identify a command acquisition mode from a plurality of command acquisition modes of a command interface of a memory device. A state of a chip select signal (CS) is identified. When the CS transitions to low from high, a first portion of a command address is captured in a first clock cycle after the CS transitions. When the command acquisition mode is in a first mode, a second portion of the command address is captured in a second clock cycle immediately after the first clock cycle. Otherwise, when the command acquisition mode is in a second mode, the second portion of the command address is captured in a third clock cycle immediately following the second clock signal. An internal command is fired, using the first portion of the command address and the second portion of the command address.

Abstract: A semiconductor device includes a clock gating tree comprising a first clock gating stage and a second clock gating stage. The first clock gating stage is configured to receive an activate detection signal and to activate clocking events in the second clock gating stage in response to the activate detection signal. The clocking events are not activated in the absence of the activate detection signal.

Abstract: Disclosed are methods for reading data from a storage buffer. One such method may include retrieving a first set of data during a first period of time. The method may also include delaying data retrieval during a second period of time after the first period of time. The method may include outputting at least a portion of the first set of data during the first period of time and the second period of time. The first period of time is substantially similar to the second period of time.