Abstract: A method and apparatus for avoiding dicing chip-outs in integrated circuit die comprises: (a) providing a wafer for forming a plurality of integrated circuit die thereon; (b) forming the plurality of integrated circuit die on the wafer; and (c) forming a saw street between the integrated circuit die on the wafer to relieve cutting stress in the wafer when the integrated circuit die are separated by a dicing saw.

Abstract: An integrated circuit package and method exploit the volume enclosed by the package substrate vias. In one embodiment, an integrated circuit package includes a first substrate having electrically conductive layers formed on substantially parallel surfaces of the first substrate, a second substrate having electrically conductive layers formed on substantially parallel surfaces of the second substrate, a substrate via formed through the first substrate and the second substrate to form an electrical connection between at least two electrically conductive layers of the first substrate and between at least two electrically conductive layers of the second substrate, an electrical component having a first end and a second end inserted into the substrate via so that the first end extends at least partially inside the first substrate and the second end extends at least partially inside the second substrate, and an electrically insulating layer formed between the first substrate and the second substrate.

Abstract: A method and apparatus for avoiding dicing chip-outs in integrated circuit die comprises: (a) providing a wafer for forming a plurality of integrated circuit die thereon; (b) forming the plurality of integrated circuit die on the wafer; and (c) forming a saw street between the integrated circuit die on the wafer to relieve cutting stress in the wafer when the integrated circuit die are separated by a dicing saw.