Patents by Inventor Parthasarathy Sriram

Parthasarathy Sriram has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090204830
    Abstract: A central processing unit (CPU) can specify an initial (e.g., baseline) frequency for a clock signal used by a device to perform a task. The CPU is then placed in a reduced power mode. The device performs the task after the CPU is placed in the reduced power mode until a triggering event causes the device to send an interrupt to the CPU. In response to the interrupt, the CPU awakens to dynamically adjust the clock frequency. If the clock frequency is reset to the baseline value, then the CPU is again placed in the reduced power mode.
    Type: Application
    Filed: February 11, 2008
    Publication date: August 13, 2009
    Applicant: NVIDIA CORPORATION
    Inventors: Aleksandr Frid, Parthasarathy Sriram
  • Publication number: 20090205053
    Abstract: Efficient and effective permission confidential information protection systems and methods are described. The secure information protection systems and methods facilitate storage of confidential information in a manner safe from rogue software access. In one embodiment, a confidential information protection method is implemented in hardware and facilitates protection against software and/or Operating System hacks. In one exemplary implementation, a confidential information protection method includes setting a permission sticky bit flag to a default state upon system set up. The permission sticky bit flag access permission indication is adjusted at system reset in accordance with an initial application instruction. Access to the confidential information is restricted in accordance with the permission sticky bit and the permission sticky bit is protected from adjustments attempting to violate the permission indication.
    Type: Application
    Filed: February 11, 2008
    Publication date: August 13, 2009
    Inventors: Parthasarathy Sriram, Gordon Grigor, Shu-Jen Fang
  • Publication number: 20090204803
    Abstract: Techniques for handling a secure storage key maintain the key in an always on domain and restore the key to the encryption/decryption engine when the engine is turned back on. The secure storage key however is only accessible by the boot loader code, which provides a secure chain of trust. In addition, the techniques allow the secure storage key to be updated.
    Type: Application
    Filed: February 11, 2008
    Publication date: August 13, 2009
    Applicant: NVIDIA CORPORATION
    Inventors: Michael Cox, Gordon Grigor, Phillip Smith, Parthasarathy Sriram
  • Patent number: 7433981
    Abstract: An architecture is described, wherein an operation unit, such as an arithmetic unit, is used for performing a variety of repetitive tasks. The present invention includes embodiments and related methods for power and computationally efficiency in performing repetitive tasks. The system includes an operation unit and a configuration control unit that is in communication with a processor. The processor sends the configuration information to the configuration unit and the configuration unit provides configuration information to the operation unit. The method includes configuring the operation unit using the configuration unit based on the configuration information, retrieving data from a designated location upon which the operation unit operates, and producing a result that is formatted and send to a destination.
    Type: Grant
    Filed: September 30, 2005
    Date of Patent: October 7, 2008
    Assignee: Nvidia Corporation
    Inventors: Robert Quan, Parthasarathy Sriram
  • Patent number: 7372379
    Abstract: This application provides a flexible and efficient way to handle escape symbols during decoding of N-tuple variable length codes (VLCs). The user can request that the decoder resolve a sequence of symbols. The Huffman lookup tables can contain a field to notify the decoder if a given N-tuple VLC includes an escape symbol. For non-escape symbols, as identified by the escape indicator bit in the Huffman lookup table entry, the decoder can finish resolving the N symbols of the N-tuple without requiring a symbol-by-symbol comparison of each symbol to detect escape conditions. For escape symbols, as identified by the escape indicator bit in the Huffman lookup table entry, the decoder can either look back to the user for help, or use pre-defined logic to resolve the escape symbols. Aspects of certain embodiments enable parallelism between Huffman symbol decoding and escape condition detection without losing future expandability.
    Type: Grant
    Filed: March 28, 2006
    Date of Patent: May 13, 2008
    Assignee: NVIDIA Corporation
    Inventors: Wei Jia, Parthasarathy Sriram, Jessica Fang
  • Patent number: 7321697
    Abstract: Method and system for lossless compression coding of a digitally represented image. The image is expressed as one or more blocks, each block having a sequence of pixels with binary pixel values. Within each block, a predictor index is chosen that predicts a pixel value as a linear combination of adjacent (actual) pixel values. The predicted and actual values are compared, and twice the predicted value is compared with the sum of the actual value and a maximum predicted value, to determine a value index, which is used to represent each pixel value in a block in compressed format. Use of the value index representation reduces the average number of bits needed to express each pixel value by an estimated 33-46 percent, reduces the time required for compression encoding by an estimated 4-6 percent, and reduces the time required for decompression by an estimated 49-61 percent.
    Type: Grant
    Filed: October 8, 2003
    Date of Patent: January 22, 2008
    Assignee: Sun Microsystems, Inc.
    Inventors: Subramania Sudharsanan, Parthasarathy Sriram
  • Publication number: 20070285285
    Abstract: A system for compressing digital data by representing a portion of it predictionally and transformationally as a block of transform coefficients, then quantizing that block selectively into a set of encoding symbols based on an indication whether the transform coefficients represent the portion as having a particular characteristic, and then by encoding the set of encoding symbols into a data bit stream. In particular, frequency may be used as the characteristic of the digital data in many applications.
    Type: Application
    Filed: June 8, 2006
    Publication date: December 13, 2007
    Applicant: PORTAL PLAYER, INC.
    Inventors: Rohit Puri, Parthasarathy Sriram
  • Publication number: 20070237231
    Abstract: In some embodiments, a video processing system including video processor, an external memory, and an integrated circuit that implements both a memory controller (having embedded intelligence) and an internal memory coupled to the memory controller. The memory controller is configured to pre-cache in the internal memory partial frames of reference video data in the external memory (e.g., N-line slices of M-line reference frames, where M>N), and to respond to requests (e.g., from the video processor) for blocks of reference video data including by determining whether each requested block (or each of at least two portions thereof) has been pre-cached in the internal memory, causing each requested cached block (or portion thereof) to be read from the internal memory, and causing each requested non-cached block (or portion thereof) to be read from the external memory.
    Type: Application
    Filed: March 29, 2006
    Publication date: October 11, 2007
    Inventors: Parthasarathy Sriram, Han Chou
  • Publication number: 20060239355
    Abstract: Both distortion rate and bit-rate can be considered together when selecting a lowest cost motion estimation signal. A motion estimation signal is generated for each of the candidate motion vectors and candidate mode information vectors for a macroblock. An estimated amount of encoding bits is determined for each of the candidate motion vectors, candidate mode information vectors, and quantized coefficients. A bit-rate is computed based on the estimated amount of encoding bits. In addition, a current macroblock is reconstructed with each of the candidate vectors, and distortion measured between each of the reconstructions and the current macroblock. A sum is computed for each distortion measurement and corresponding bit-rate. The lowest sum represents the lowest cost motion estimation signal.
    Type: Application
    Filed: July 3, 2006
    Publication date: October 26, 2006
    Applicant: SUN MICROSYSTEMS, INC.
    Inventors: Parthasarathy Sriram, Subramania Sudharsanan
  • Patent number: 7072397
    Abstract: The present invention involves a system and method for performing motion estimation. For each candidate motion vector, encoding distortion is determined between a macroblock and a reconstructed macroblock by determining discrete cosine transform coefficients of the macroblock and quantizing the discrete cosine transform coefficients. An estimate unit determines the length of the bit stream required to encode the quantized discrete cosine transform coefficients along with the mode information bits including mode and motion vector information. The reconstructed macroblock is determined based on the quantized discrete cosine transform coefficients. A bit-rate term based on the length of the bit-rate stream is determined and included in the encoding distortion. The candidate motion vector which minimizes the encoding distortion of the macroblock is chosen to be the motion vector for the macroblock.
    Type: Grant
    Filed: May 29, 2002
    Date of Patent: July 4, 2006
    Assignee: Sun Microsystems, Inc.
    Inventors: Parthasarathy Sriram, Subramania Sudharsanan
  • Patent number: 6965641
    Abstract: A method of assigning a buffer size in a video decoder includes the step of establishing a first buffer size for a scalable buffer. A video data stream is then processed with the scalable buffer configured to the first buffer size. A second buffer size is then selected for the scalable buffer. The video stream is then processed with the scalable buffer configured to the second buffer size. Memory utilization data characterizing memory performance during processing with the scalable buffer at the first buffer size and the second buffer size is then created. Afterwards, a buffer size is assigned for the scalable buffer in accordance with the memory utilization data.
    Type: Grant
    Filed: March 2, 2000
    Date of Patent: November 15, 2005
    Assignee: Sun Microsystems, Inc.
    Inventors: Amit Gulati, Subramania I. Sudharsanan, Parthasarathy Sriram
  • Patent number: 6731686
    Abstract: A method for pipelining variable length decode and inverse quantization operations in a hybrid motion-compensated and transform coded video decoder includes the step of mapping a new code word to a look-up table to retrieve a code word length, a zero-run length, and a quantized level. A new linear, zig-zagged position of a current coefficient is identified from the zero-run length and a previous zero-run length. The code word length is added to a current bitstream position to yield a new bitstream position. A quantization matrix coefficient from the new linear, zig-zagged position of the current coefficient is selected. The quantized level is multiplied by a predetermined value to produce a quantization product. In the case of inter block processing, a quantized level sign value is added to the quantization product. In the case of intra block processing, the quantization product does not include the quantization level sign.
    Type: Grant
    Filed: May 31, 2000
    Date of Patent: May 4, 2004
    Assignee: Sun Microsystems, Inc.
    Inventors: Subramania I. Sudharsanan, Parthasarathy Sriram, Amit Gulati
  • Publication number: 20040071356
    Abstract: Method and system for lossless compression coding of a digitally represented image. The image is expressed as one or more blocks, each block having a sequence of pixels with binary pixel values. Within each block, a predictor index is chosen that predicts a pixel value as a linear combination of adjacent (actual) pixel values. The predicted and actual values are compared, and twice the predicted value is compared with the sum of the actual value and a maximum predicted value, to determine a value index, which is used to represent each pixel value in a block in compressed format. Use of the value index representation reduces the average number of bits needed to express each pixel value by an estimated 33-46 percent, reduces the time required for compression encoding by an estimated 4-6 percent, and reduces the time required for decompression by an estimated 49-61 percent.
    Type: Application
    Filed: October 8, 2003
    Publication date: April 15, 2004
    Inventors: Subramania Sudharsanan, Parthasarathy Sriram
  • Patent number: 6668092
    Abstract: A lossless compression mechanism for compressing and restoring data elements such as text, text formatting, video, audio, speech, and 2D and 3D graphical information. Each data element is compressed using a data structure having a bin number field and an offset field. The bin number field is associated to a bin having a range of values which includes the data element value. The offset field is computed from a minimum bin value, wherein the minimum bin value is associated to the bin and is stored in a bin lookup table. The bin number field is encoded using a unary code, and the offset is encoded using a binary code.
    Type: Grant
    Filed: July 30, 1999
    Date of Patent: December 23, 2003
    Assignee: Sun Microsystems, Inc.
    Inventors: Parthasarathy Sriram, Subramania Sudharsanan
  • Patent number: 6654419
    Abstract: Method and system for compression coding of a digitally represented video image. The video image is expressed as one or more data blocks in two or more frames, each block having a sequence of pixels with pixel values. Within each block of a frame, an intra-frame predictor index or inter-frame predictor index is chosen that predicts a pixel value as a linear combination of actual pixel values, drawn from one frame or from two or more adjacent frames. The predicted and actual pixel values are compared, and twice the predicted value is compared with the sum of the actual value and a maximum predicted value, to determine a value index, which is used to represent each pixel value in a block in compressed format in each frame. The compression ratios achieved by this coding approach compare favorably with, and may improve upon, the compression achieved by other compression methods.
    Type: Grant
    Filed: April 28, 2000
    Date of Patent: November 25, 2003
    Assignee: Sun Microsystems, Inc.
    Inventors: Parthasarathy Sriram, Subramania Sudharsanan
  • Patent number: 6654503
    Abstract: Method and system for lossless compression coding of a digitally represented image. The image is expressed as one or more blocks, each block having a sequence of pixels with binary pixel values. Within each block, a predictor index is chosen that predicts a pixel value as a linear combination of adjacent (actual) pixel values. The predicted and actual values are compared, and twice the predicted value is compared with the sum of the actual value and a maximum predicted value, to determine a value index, which is used to represent each pixel value in a block in compressed format. Use of the value index representation reduces the average number of bits needed to express each pixel value by an estimated 33-46 percent, reduces the time required for compression encoding by an estimated 4-6 percent, and reduces the time required for decompression by an estimated 49-61 percent.
    Type: Grant
    Filed: April 28, 2000
    Date of Patent: November 25, 2003
    Assignee: Sun Microsystems, Inc.
    Inventors: Subramania Sudharsanan, Parthasarathy Sriram
  • Patent number: 6603813
    Abstract: A compression system and process employs a group of quantizers (or set of predefined quantized values) and involves the selection of the quantizers for each video frame or frame portion. For each frame portion, a selection of the most appropriate quantizer is made. The selection of which quantizer from the selection group is most appropriate for coding of a video frame or frame portion is based on a formula which takes account both the distortion (accuracy) and bit rate characteristics of each quantizer. The quantizer that exhibits the best combined distortion and bit rate characteristics is selected for coding the frame or frame portion. A similar formula, based on both distortion and bit rate characteristics, is used to select the particular quantization value within the quantizer set for each video signal value being coded.
    Type: Grant
    Filed: November 3, 1999
    Date of Patent: August 5, 2003
    Assignee: Conexant Systems, Inc.
    Inventors: Parthasarathy Sriram, Anurag Bist
  • Publication number: 20030063667
    Abstract: The present invention involves a system and method for performing motion estimation. For each candidate motion vector, encoding distortion is determined between a macroblock and a reconstructed macroblock by determining discrete cosine transform cofficients of the macroblock and quantizing the discrete cosine transform coefficients. An estimate unit determines the length of the bit stream required to encode the quantized discrete cosine transform coefficients along with the mode information bits including mode and motion vector information. The reconstructed macroblock is determined based on the quantized discrete cosine transform coefficients. A bit-rate term based on the length of the bit-rate stream is determined and included in the encoding distortion. The candidate motion vector which minimizes the encoding distortion of the macroblock is chosen to be the motion vector for the macroblock.
    Type: Application
    Filed: May 29, 2002
    Publication date: April 3, 2003
    Applicant: Sun Microsystems, Inc.
    Inventors: Parthasarathy Sriram, Subramania Sudharsanan
  • Patent number: 6539059
    Abstract: An apparatus for decoding a Motion Compensated-Discrete Cosine Transform (MC-DCT) video stream includes an input port to receive an MC-DCT video stream with an associated hierarchy of data structures including a sequence data structure, a picture data structure, a slice data structure, and a macroblock data structure. A monitor processor splits the MC-DCT video stream into a set of video streams. A set of sub-processors processes the set of video streams. Each sub-processor has an assigned computational task performed on a specified hierarchical level of the associated hierarchy of data structures. Each sub-processor performs the assigned computational task with a designated data structure including all parameter data required at the specified hierarchical level.
    Type: Grant
    Filed: March 2, 2000
    Date of Patent: March 25, 2003
    Assignee: Sun Microsystems, Inc.
    Inventors: Parthasarathy Sriram, Subramania I. Sudharsanan, Amit Gulati
  • Patent number: 6414992
    Abstract: The present invention involves a system and method for optimizing video encoding. For each candidate motion vector, encoding distortion is determined between a macroblock and a reconstructed macroblock by determining discrete cosine transform coefficients of the macroblock and quantizing the discrete cosine transform coefficients. An estimate unit estimates the length of the bit stream that would be required to encode the quantized discrete cosine transform coefficients along with the mode information bits including mode and motion vector information. The reconstructed macroblock is determined based on the quantized discrete cosine transform coefficients. A bit-rate term based on the length of the bit-rate stream is determined and included in the encoding distortion. The candidate motion vector which minimizes the encoding distortion of the macroblock is chosen to be the motion vector for the macroblock.
    Type: Grant
    Filed: January 27, 1999
    Date of Patent: July 2, 2002
    Assignee: Sun Microsystems, Inc.
    Inventors: Parthasarathy Sriram, Subramania Sudharsanan