Patents by Inventor Parthiv Pota
Parthiv Pota has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11829764Abstract: Techniques are disclosed for address manipulation using indices and tags. A first index is generated from bits of a processor program counter, where the first index is used to access a branch predictor bimodal table. A first branch prediction is provided from the bimodal table, based on the first index. The first branch prediction is matched against N tables, where the tables contain prior branch histories, and where: the branch history in table T(N) is of greater length than the branch history of table T(N-1), and the branch history in table T(N-1) is of greater length than the branch history of table T(N-2). A processor address is manipulated using a greatest length of hits of branch prediction matches from the N tables, based on one or more hits occurring. The branch predictor address is manipulated using the first branch prediction from the bimodal table, based on zero hits occurring.Type: GrantFiled: March 7, 2023Date of Patent: November 28, 2023Assignee: MIPS Tech, LLCInventors: Parthiv Pota, Sanjay Patel, Raj Kumar Singh Parihar
-
Publication number: 20230205534Abstract: Techniques are disclosed for address manipulation using indices and tags. A first index is generated from bits of a processor program counter, where the first index is used to access a branch predictor bimodal table. A first branch prediction is provided from the bimodal table, based on the first index. The first branch prediction is matched against N tables, where the tables contain prior branch histories, and where: the branch history in table T(N) is of greater length than the branch history of table T(N-1), and the branch history in table T(N-1) is of greater length than the branch history of table T(N-2). A processor address is manipulated using a greatest length of hits of branch prediction matches from the N tables, based on one or more hits occurring. The branch predictor address is manipulated using the first branch prediction from the bimodal table, based on zero hits occurring.Type: ApplicationFiled: March 7, 2023Publication date: June 29, 2023Inventors: Parthiv Pota, Sanjay Patel, Raj Kumar Singh Parihar
-
Patent number: 11635963Abstract: Techniques are disclosed for address manipulation using indices and tags. A first index is generated from bits of a processor program counter, where the first index is used to access a branch predictor bimodal table. A first branch prediction is provided from the bimodal table, based on the first index. The first branch prediction is matched against N tables, where the tables contain prior branch histories, and where: the branch history in table T(N) is of greater length than the branch history of table T(N-1), and the branch history in table T(N-1) is of greater length than the branch history of table T(N-2). A processor address is manipulated using a greatest length of hits of branch prediction matches from the N tables, based on one or more hits occurring. The branch predictor address is manipulated using the first branch prediction from the bimodal table, based on zero hits occurring.Type: GrantFiled: June 30, 2021Date of Patent: April 25, 2023Assignee: MIPS Tech, LLCInventors: Parthiv Pota, Sanjay Patel, Raj Kumar Singh Parihar
-
Publication number: 20210373897Abstract: Techniques are disclosed for address manipulation using indices and tags. A first index is generated from bits of a processor program counter, where the first index is used to access a branch predictor bimodal table. A first branch prediction is provided from the bimodal table, based on the first index. The first branch prediction is matched against N tables, where the tables contain prior branch histories, and where: the branch history in table T(N) is of greater length than the branch history of table T(N-1), and the branch history in table T(N-1) is of greater length than the branch history of table T(N-2). A processor address is manipulated using a greatest length of hits of branch prediction matches from the N tables, based on one or more hits occurring. The branch predictor address is manipulated using the first branch prediction from the bimodal table, based on zero hits occurring.Type: ApplicationFiled: June 30, 2021Publication date: December 2, 2021Inventors: Parthiv Pota, Sanjay Patel, Raj Kumar Singh Parihar
-
Patent number: 11080062Abstract: Techniques are disclosed for address manipulation using indices and tags. A first index is generated from bits of a processor program counter, where the first index is used to access a branch predictor bimodal table. A first branch prediction is provided from the bimodal table, based on the first index. The first branch prediction is matched against N tables, where the tables contain prior branch histories, and where: the branch history in table T(N) is of greater length than the branch history of table T(N?1), and the branch history in table T(N?1) is of greater length than the branch history of table T(N?2). A processor address is manipulated using a greatest length of hits of branch prediction matches from the N tables, based on one or more hits occurring. The branch predictor address is manipulated using the first branch prediction from the bimodal table, based on zero hits occurring.Type: GrantFiled: January 10, 2020Date of Patent: August 3, 2021Assignee: MIPS Tech, LLCInventors: Parthiv Pota, Sanjay Patel, Raj Kumar Singh Parihar
-
Publication number: 20200225955Abstract: Techniques are disclosed for address manipulation using indices and tags. A first index is generated from bits of a processor program counter, where the first index is used to access a branch predictor bimodal table. A first branch prediction is provided from the bimodal table, based on the first index. The first branch prediction is matched against N tables, where the tables contain prior branch histories, and where: the branch history in table T(N) is of greater length than the branch history of table T(N?1), and the branch history in table T(N?1) is of greater length than the branch history of table T(N?2). A processor address is manipulated using a greatest length of hits of branch prediction matches from the N tables, based on one or more hits occurring. The branch predictor address is manipulated using the first branch prediction from the bimodal table, based on zero hits occurring.Type: ApplicationFiled: January 10, 2020Publication date: July 16, 2020Inventors: Parthiv Pota, Sanjay Patel, Raj Kumar Singh Parihar
-
Patent number: 10664280Abstract: A fetch ahead branch target buffer is used by a branch predictor to determine a target address for a branch instruction based on a fetch pointer for a previous fetch bundle, i.e. a fetch bundle which is fetched prior to a fetch bundle which includes the branch instruction. An entry in the fetch ahead branch target buffer corresponds to one branch instruction and comprises a data portion identifying the target address of that branch instruction. In various examples, an entry also comprises a tag portion which stores data identifying the fetch pointer by which the entry is indexed. Branch prediction is performed by matching an index generated using a received fetch pointer to the tag portions to identify a matching entry and then determining the target address for the branch instruction from the data portion of the matching entry.Type: GrantFiled: November 9, 2015Date of Patent: May 26, 2020Assignee: MIPS Tech, LLCInventors: Parthiv Pota, Sanjay Patel, Sudhakar Ranganathan
-
Patent number: 10540179Abstract: A processor is configured to identify a branch instruction immediately followed by an architectural delay slot. A single bonded instruction comprising the branch instruction immediately followed by the architectural delay slot is created. The single bonded instruction is loaded into an instruction buffer.Type: GrantFiled: March 7, 2013Date of Patent: January 21, 2020Assignee: MIPS Tech, LLCInventors: Ranganathan Sudhakar, Parthiv Pota
-
Patent number: 9720840Abstract: Methods and systems that identify and power up ways for future instructions are provided. A processor includes an n-way set associative cache and an instruction fetch unit. The n-way set associative cache is configured to store instructions. The instruction fetch unit is in communication with the n-way set associative cache and is configured to power up a first way, where a first indication is associated with an instruction and indicates the way where a future instruction is located and where the future instruction is two or more instructions ahead of the current instruction.Type: GrantFiled: February 28, 2013Date of Patent: August 1, 2017Assignee: Imagination Technologies, LLCInventors: Ranganathan Sudhakar, Parthiv Pota
-
Publication number: 20170132009Abstract: A fetch ahead branch target buffer is used by a branch predictor to determine a target address for a branch instruction based on a fetch pointer for a previous fetch bundle, i.e. a fetch bundle which is fetched prior to a fetch bundle which includes the branch instruction. An entry in the fetch ahead branch target buffer corresponds to one branch instruction and comprises a data portion identifying the target address of that branch instruction. In various examples, an entry also comprises a tag portion which stores data identifying the fetch pointer by which the entry is indexed. Branch prediction is performed by matching an index generated using a received fetch pointer to the tag portions to identify a matching entry and then determining the target address for the branch instruction from the data portion of the matching entry.Type: ApplicationFiled: November 9, 2015Publication date: May 11, 2017Inventors: Parthiv Pota, Sanjay Patel, Sudhakar Ranganathan
-
Publication number: 20140258694Abstract: A processor is configured to identify a branch instruction immediately followed by an architectural delay slot. A single bonded instruction comprising the branch instruction immediately followed by the architectural delay slot is created. The single bonded instruction is loaded into an instruction buffer.Type: ApplicationFiled: March 7, 2013Publication date: September 11, 2014Applicant: MIPS Technologies, Inc.Inventors: Ranganathan Sudhakar, Parthiv Pota
-
Publication number: 20140250289Abstract: Improved branch target buffers (BTBs) and methods of processing data in a microprocessor with a pipeline are provided. According to various embodiments, a BTB is provided that includes a non-return buffer, a return buffer, and a multiplexer. The non-return buffer is designed to store a multiple of non-return entries. Each non-return entry corresponds to a non-return type instruction. The return buffer is designed to store a plurality of return entries that each correspond to a return type instruction. Additionally, the return buffer may generate a control signal. The multiplexer also generates a control signal and outputs either data from the non-return buffer or data from a return prediction stack (RPS). Whether the multiplexer returns data from the non-return buffer or the RPS depends on the control signal.Type: ApplicationFiled: March 1, 2013Publication date: September 4, 2014Applicant: MIPS Technologies, Inc.Inventors: Parthiv POTA, Sanjay PATEL
-
Publication number: 20140244933Abstract: Methods and systems that identify and power up ways for future instructions are provided. A processor includes an n-way set associative cache and an instruction fetch unit. The n-way set associative cache is configured to store instructions. The instruction fetch unit is in communication with the n-way set associative cache and is configured to power up a first way, where a first indication is associated with an instruction and indicates the way where a future instruction is located and where the future instruction is two or more instructions ahead of the current instruction.Type: ApplicationFiled: February 28, 2013Publication date: August 28, 2014Applicant: MIPS Technologies, Inc.Inventors: Ranganathan Sudhakar, Parthiv Pota