Patents by Inventor Partia Naghibi

Partia Naghibi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230378120
    Abstract: A method to aid in a calibration of a compression system includes mounting a first substrate in a press. The press has calibration parameters, and the first substrate has a test film on a first surface. The method includes mounting a second substrate in the press. The second substrate has spikes arranged in a spike pattern on a second surface. The method includes compressing the first substrate and the second substrate together with a force that causes the spikes to form indentations in the test film, separating the first substrate from the second substrate, determining local pressures applied by the spikes against the test film, and adjusting one or more calibration parameters of the press in response to the local pressures.
    Type: Application
    Filed: May 18, 2022
    Publication date: November 23, 2023
    Applicant: The Boeing Company
    Inventors: Peter D. Brewer, Chia-Ming Chang, Partia Naghibi Mahmoudabadi, Sevag Terterian, Diego Eduardo Carrasco, Charbel Abijaoude
  • Patent number: 11769843
    Abstract: A photonic module and a method of making same, the module having one or more optoelectronic chips, such as a laser diode typically having six sides, with each optoelectronic chip having two opposing sides (a first side and a second side) abutting and electrically connected to metal regions (preferably electro-formed), the two metal regions are physically distinct and electrically separate from each other, the two electro-formed metal regions serving, in use, as heat spreaders for conducting heat away from the optoelectronic chip.
    Type: Grant
    Filed: May 29, 2020
    Date of Patent: September 26, 2023
    Assignee: HRL LABORATORIES, LLC
    Inventors: Daniel Yap, Florian G. Herrault, Christopher S. Roper, Partia Naghibi
  • Patent number: 11562984
    Abstract: A method and apparatus for laterally urging two semiconductor chips, dies or wafers into an improved state of registration with each other, the method and apparatus employing microstructures comprising: a first microstructure disposed on a first major surface of a first one of said two semiconductor chips, dies or wafers, wherein the first microstructure includes a sidewall which is tapered thereby disposing it at an acute angle compared to a perpendicular of said first major surface, and a second microstructure disposed on a first surface of a second one of said two semiconductor chips, dies or wafers, wherein the shape of the second microstructure is complementary to, and mates with or contacts, in use, the first microstructure, the second microstructure including a surface which contacts said sidewall when the first and second microstructures are mated or being mated, the sidewall of the first microstructure and the surface of the second microstructure imparting a lateral force for urging the two semicondu
    Type: Grant
    Filed: October 14, 2020
    Date of Patent: January 24, 2023
    Assignee: HRL LABORATORIES, LLC
    Inventors: Peter Brewer, Aurelio Lopez, Partia Naghibi-Mahmoudabadi, Tahir Hussain
  • Publication number: 20190237400
    Abstract: An integrated component having a metallic interlocking structure; the integrated component comprising an integrated circuit integrated in a substrate having a top surface; the integrated circuit comprising a first conducting line; and a first metallic interlocking structure comprising a first array of free-standing metallic columns formed on said top surface and electrically connected to said first conducting line.
    Type: Application
    Filed: December 7, 2018
    Publication date: August 1, 2019
    Applicant: HRL Laboratories, LLC
    Inventors: Florian G HERRAULT, Joel C. Wong, Helen Hor Ka. Fung, Partia Naghibi-Mahmoudabadi