Abstract: A circuit that stabilizes an output signal of a voltage regulator includes a glitch amplifier, a pulse generator, and a transistor. The glitch amplifier amplifies glitches in the output signal and generates a glitch amplifier output signal. The pulse generator receives the glitch amplifier output signal and generates a control signal. When there is a positive glitch in the output signal and a voltage level of the glitch amplifier output signal is less than a first threshold voltage, the pulse generator deactivates the control signal, which turns off the transistor. When there is a negative glitch in the output signal and the voltage level of the glitch amplifier output signal is greater than a second threshold voltage, the pulse generator activates the control signal, which turns on the transistor and provides a compensating current surge to reduce a voltage droop in the output signal.

Abstract: A circuit that stabilizes an output signal of a voltage regulator includes a glitch amplifier, a pulse generator, and a transistor. The glitch amplifier amplifies glitches in the output signal and generates a glitch amplifier output signal. The pulse generator receives the glitch amplifier output signal and generates a control signal. When there is a positive glitch in the output signal and a voltage level of the glitch amplifier output signal is less than a first threshold voltage, the pulse generator deactivates the control signal, which turns off the transistor. When there is a negative glitch in the output signal and the voltage level of the glitch amplifier output signal is greater than a second threshold voltage, the pulse generator activates the control signal, which turns on the transistor and provides a compensating current surge to reduce a voltage droop in the output signal.

Abstract: A voltage regulator includes an error amplifier, a voltage buffer, a transistor, a frequency compensation circuit, a capacitor, and a resistive network. The error amplifier receives a reference signal and a feedback signal, and generates an intermediate control signal. The voltage buffer receives the intermediate control signal and generates a control signal. The transistor has a gate that receives the control signal, a first terminal that receives a supply voltage signal, and a second terminal that generates a regulated output signal. The frequency compensation circuit is connected to the second terminal of the transistor. The capacitor is connected to the error amplifier and the frequency compensation circuit. The resistive network receives the regulated output signal and generates the feedback signal.

Abstract: A voltage regulator includes an error amplifier, a voltage buffer, a transistor, a frequency compensation circuit, a capacitor, and a resistive network. The error amplifier receives a reference signal and a feedback signal, and generates an intermediate control signal. The voltage buffer receives the intermediate control signal and generates a control signal. The transistor has a gate that receives the control signal, a first terminal that receives a supply voltage signal, and a second terminal that generates a regulated output signal. The frequency compensation circuit is connected to the second terminal of the transistor. The capacitor is connected to the error amplifier and the frequency compensation circuit. The resistive network receives the regulated output signal and generates the feedback signal.

Abstract: A Universal Serial Bus (USB) controller includes a USB transceiver to detect a high-speed (HS) disconnect between the USB controller and a device connected to it. The USB transceiver includes a reference-voltage generation circuit, a HS current driver, first and second comparators, and a multiplexer. The reference-voltage generation circuit generates HS disconnect and transmitter reference-voltage signals that have a constant voltage difference. The first comparator receives DP and DM signals that correspond to a HS Start of Frame (SOF) packet during HS disconnect detection, and generates a control voltage. The multiplexer outputs at least one of the DP and DM signals based on the logic state of the control voltage. The second comparator receives the selected signal and the HS disconnect reference-voltage signal, and outputs a HS disconnect output voltage signal when the selected signal is greater than the HS disconnect reference-voltage signal.

Abstract: A Universal Serial Bus (USB) controller includes a USB transceiver to detect a high-speed (HS) disconnect between the USB controller and a device connected to it. The USB transceiver includes a reference-voltage generation circuit, a HS current driver, first and second comparators, and a multiplexer. The reference-voltage generation circuit generates HS disconnect and transmitter reference-voltage signals that have a constant voltage difference. The first comparator receives DP and DM signals that correspond to a HS Start of Frame (SOF) packet during HS disconnect detection, and generates a control voltage. The multiplexer outputs at least one of the DP and DM signals based on the logic state of the control voltage. The second comparator receives the selected signal and the HS disconnect reference-voltage signal, and outputs a HS disconnect output voltage signal when the selected signal is greater than the HS disconnect reference-voltage signal.

Abstract: A voltage clamping circuit that is implemented using low voltage devices provides a way to discharge an input/output pin to ground during overvoltage conditions and to avoid any interaction between the input/output pin and the input/output supply during clamping action. The voltage clamping circuit is also self-protected. A voltage detection circuit detects an overvoltage condition and in response generates a signal that turns on a PMOS, which in turn provides a clamping current path between the input/output pin and ground.

Abstract: A voltage clamping circuit that is implemented using low voltage devices provides a way to discharge an input/output pin to ground during overvoltage conditions and to avoid any interaction between the input/output pin and the input/output supply during clamping action. The voltage clamping circuit is also self-protected. A voltage detection circuit detects an overvoltage condition and in response generates a signal that turns on a PMOS, which in turn provides a clamping current path between the input/output pin and ground.

Abstract: A circuit for scaling down first and second input voltages includes first and second voltage scale-down circuits that scale down the first and second input voltages, respectively. The first voltage scale-down circuit includes a transistor that receives the first input voltage at its gate and, operating in a source-follower configuration, scales down the first input voltage to generate a first output voltage at its source. The second voltage scale-down circuit is identical to the first voltage scale-down circuit and generates a second output voltage based on the second input voltage.

Abstract: A circuit for scaling down first and second input voltages includes first and second voltage scale-down circuits that scale down the first and second input voltages, respectively. The first voltage scale-down circuit includes a transistor that receives the first input voltage at its gate and, operating in a source-follower configuration, scales down the first input voltage to generate a first output voltage at its source. The second voltage scale-down circuit is identical to the first voltage scale-down circuit and generates a second output voltage based on the second input voltage.

Abstract: A data processing device with a power supply and data signal interface circuit has a switch for connecting an external line and an internal node. The power supply and data signal interface circuit also includes a controller for applying an enabling voltage to the switch enabling the switch to supply current between the external line and the internal node in the presence of power supply to the controller and in the absence of the overvoltage condition on the external line. The power supply and data signal interface circuit also includes a voltage reduction connection from the external line for applying a control voltage to the switch in the absence of power supply to the controller. The control voltage from the voltage reduction connection limits a voltage applied to the internal node through the switch in the presence of the overvoltage condition.

Abstract: An embedded system includes a level shifter circuit for generating a forward supply voltage level in a predefined range. A sense circuit senses a core supply voltage level of the embedded system and compares the sensed core supply voltage level with a predetermined minimum core supply voltage level needed to generate the forward supply voltage. A reset circuit maintains one or more input nodes and one or more internal nodes of the level shifter circuit at a predetermined voltage level when the core supply voltage level is less than the predetermined minimum core supply voltage level.

Abstract: A voltage clamping circuit for protecting an input/output (I/O) terminal of an integrated circuit from over shoot and under shoot voltages includes transistors connected to form a current conducting path. A voltage at the I/O pin is detected using a voltage detection circuit. The current conducting path is switched on when the voltage at the I/O pin exceeds a predetermined value.

Abstract: An embedded system includes a level shifter circuit for generating a forward supply voltage level in a predefined range. A sense circuit senses a core supply voltage level of the embedded system and compares the sensed core supply voltage level with a predetermined minimum core supply voltage level needed to generate the forward supply voltage. A reset circuit maintains one or more input nodes and one or more internal nodes of the level shifter circuit at a predetermined voltage level when the core supply voltage level is less than the predetermined minimum core supply voltage level.

Abstract: A data processing device with a power supply and data signal interface circuit has a switch for connecting an external line and an internal node. The power supply and data signal interface circuit also includes a controller for applying an enabling voltage to the switch enabling the switch to supply current between the external line and the internal node in the presence of power supply to the controller and in the absence of the overvoltage condition on the external line. The power supply and data signal interface circuit also includes a voltage reduction connection from the external line for applying a control voltage to the switch in the absence of power supply to the controller. The control voltage from the voltage reduction connection limits a voltage applied to the internal node through the switch in the presence of the overvoltage condition.

Abstract: A USB system includes a USB hub, a USB device, and a USB bus interconnecting the USB hub and the USB device. The USB hub asserts a reset signaling on the USB bus to initiate a high-speed detection handshake. The USB hub and the USB device activate corresponding dual-mode squelch detectors in a first (handshake) mode of operation. The USB device transmits a device chirp signal to the USB hub. The USB hub responds with a sequence of hub chirp signals. The USB device detects the hub chirp signals and then the USB hub and the USB device establish a communication link in a high-speed mode of communication in accordance with USB 2.0. The dual-mode squelch detectors in the USB hub and the USB device can also be activated in a second (normal) mode of operation.

Abstract: A USB system includes a USB hub, a USB device, and a USB bus interconnecting the USB hub and the USB device. The USB hub asserts a reset signaling on the USB bus to initiate a high-speed detection handshake. The USB hub and the USB device activate corresponding dual-mode squelch detectors in a first (handshake) mode of operation. The USB device transmits a device chirp signal to the USB hub. The USB hub responds with a sequence of hub chirp signals. The USB device detects the hub chirp signals and then the USB hub and the USB device establish a communication link in a high-speed mode of communication in accordance with USB 2.0. The dual-mode squelch detectors in the USB hub and the USB device can also be activated in a second (normal) mode of operation.