Patents by Inventor Parvathy SASIKALA JAYACHANDRAN PILLAI

Parvathy SASIKALA JAYACHANDRAN PILLAI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Analog-to-digital converter, measurement arrangement and method for analog-to-digital conversion
    Patent number: 10826523
    Abstract: An analog-to-digital converter (10) comprises a first and a second sampling capacitor (24, 25), a first integrator (26), a first and a second input switch (31, 32) coupling a first input terminal (11) and a common mode terminal (39) to a first electrode of the first sampling capacitor (24), a third and a fourth input switch (33, 34) coupling a second input terminal (12) and the common mode terminal (39) to a first electrode of the second sampling capacitor (25), a fifth and a sixth input switch (35, 36) coupling a second electrode of the first sampling capacitor (24) to an amplifier common mode terminal (40) and the first integrator input (27), and a seventh and an eighth input switch (37, 38) coupling a second electrode of the second sampling capacitor (25) to the amplifier common mode terminal (40) and the second integrator input (28).
    Type: Grant
    Filed: May 4, 2018
    Date of Patent: November 3, 2020
    Assignee: ams AG
    Inventors: Ravi Kumar Adusumalli, Sudhakar Singamala, Veeresh Babu Vulligaddala, Rohit Ranganathan, Chandra Nyshadham, Krishna Kanth Avalur, Parvathy Sasikala Jayachandran Pillai
  • ANALOG-TO-DIGITAL CONVERTER, MEASUREMENT ARRANGEMENT AND METHOD FOR ANALOG-TO-DIGITAL CONVERSION
    Publication number: 20200083901
    Abstract: An analog-to-digital converter (10) comprises a first and a second sampling capacitor (24, 25), a first integrator (26), a first and a second input switch (31, 32) coupling a first input terminal (11) and a common mode terminal (39) to a first electrode of the first sampling capacitor (24), a third and a fourth input switch (33, 34) coupling a second input terminal (12) and the common mode terminal (39) to a first electrode of the second sampling capacitor (25), a fifth and a sixth input switch (35, 36) coupling a second electrode of the first sampling capacitor (24) to an amplifier common mode terminal (40) and the first integrator input (27), and a seventh and an eighth input switch (37, 38) coupling a second electrode of the second sampling capacitor (25) to the amplifier common mode terminal (40) and the second integrator input (28).
    Type: Application
    Filed: May 4, 2018
    Publication date: March 12, 2020
    Inventors: Ravi Kumar ADUSUMALLI, Sudhakar Singamala, Veeresh Babu VULLIGADDALA, Rohit RANGANATHAN, Chandra NYSHADHAM, Krishna Kanth AVALUR, Parvathy SASIKALA JAYACHANDRAN PILLAI