Patents by Inventor Parviz Keshtbod
Parviz Keshtbod has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9558802Abstract: A method of programming an MTJ includes selecting an MTJ that is coupled to an access transistor at the drain of the access transistor. The gate of the access transistor is coupled to a selected word line (WL), the selected WL being substantially at a first voltage, Vdd; whereas the WLs that are not coupled to the MTJ are left to float. A second voltage, Vx, is applied to the unselected bit lines (BLs) and further applied to a source line (SL), the SL being coupled to the source of the access transistor. A third voltage, Vdd or 0 Volts, is applied to a selected BL, the selected BL being coupled the MTJ. The first voltage is applied to a SL, the SL being coupled to the source of the access transistor thereby causing the WL to boot above the first voltage.Type: GrantFiled: July 6, 2016Date of Patent: January 31, 2017Assignee: Avalanche Technology, Inc.Inventors: Ebrahim Abedifard, Parviz Keshtbod
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Publication number: 20160314828Abstract: A method of programming an MTJ includes selecting an MTJ that is coupled to an access transistor at the drain of the access transistor. The gate of the access transistor is coupled to a selected word line (WL), the selected WL being substantially at a first voltage, Vdd; whereas the WLs that are not coupled to the MTJ are left to float. A second voltage, Vx, is applied to the unselected bit lines (BLs) and further applied to a source line (SL), the SL being coupled to the source of the access transistor. A third voltage, Vdd or 0 Volts, is applied to a selected BL, the selected BL being coupled the MTJ. The first voltage is applied to a SL, the SL being coupled to the source of the access transistor thereby causing the WL to boot above the first voltage.Type: ApplicationFiled: July 6, 2016Publication date: October 27, 2016Inventors: Ebrahim Abedifard, Parviz Keshtbod
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Patent number: 9478279Abstract: The present invention is directed to a multi-state current-switching magnetic memory element configured to store a state by current flowing therethrough to switch the state including two or more magnetic tunneling junctions (MTJs) coupled in parallel between a top electrode and a bottom electrode. Each MTJ includes a free layer with a switchable magnetic orientation perpendicular to a layer plane thereof, a fixed layer with a fixed magnetic orientation perpendicular to a layer plane thereof, and a barrier layer interposed between the free layer and the fixed layer. The magnetic memory element is operable to store more than one bit of information.Type: GrantFiled: May 6, 2016Date of Patent: October 25, 2016Assignee: Avalanche Technology, Inc.Inventors: Rajiv Yadav Ranjan, Parviz Keshtbod, Roger Klas Malmhall
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Publication number: 20160254046Abstract: The present invention is directed to a multi-state current-switching magnetic memory element configured to store a state by current flowing therethrough to switch the state including two or more magnetic tunneling junctions (MTJs) coupled in parallel between a top electrode and a bottom electrode. Each MTJ includes a free layer with a switchable magnetic orientation perpendicular to a layer plane thereof, a fixed layer with a fixed magnetic orientation perpendicular to a layer plane thereof, and a barrier layer interposed between the free layer and the fixed layer. The magnetic memory element is operable to store more than one bit of information.Type: ApplicationFiled: May 6, 2016Publication date: September 1, 2016Inventors: Rajiv Yadav Ranjan, Parviz Keshtbod, Roger Klas Malmhall
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Patent number: 9401194Abstract: A method of programming a MTJ includes selecting a MTJ that is coupled to an access transistor at the drain of the access transistor. The gate of the access transistor is coupled to a selected word line (WL), the selected WL is substantially at a first voltage, Vdd; whereas the WLs that are not coupled to the MTJ are left to float. A second voltage, Vx, is applied to the unselected bit lines (BLs) and further applied to a source line (SL), the SL being coupled to the source of the access transistor. A third voltage, Vdd or 0 Volts, is applied to a selected BL, the selected BL is coupled the MTJ. The first voltage is applied to a SL, the SL is coupled to the source of the access transistor thereby causing the WL to boot above the first voltage.Type: GrantFiled: April 15, 2014Date of Patent: July 26, 2016Assignee: Avalanche Technology, Inc.Inventors: Ebrahim Abedifard, Parviz Keshtbod
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Patent number: 9349941Abstract: The present invention is directed to a multi-state current-switching magnetic memory element configured to store a state by current flowing therethrough to switch the state. The magnetic memory element includes a stack of two or more magnetic tunneling junctions (MTJs) with each MTJ including a free layer with a switchable magnetic orientation perpendicular to a layer plane thereof, a barrier layer, and a fixed layer with a fixed magnetic orientation perpendicular to a layer plane thereof. Each MTJ is separated from other MTJs in the stack by at least an isolation layer. The stack of MTJs may store more than one bit of information. The free layer of each MTJ has a switching current threshold different from free layers of other MTJs in the stack.Type: GrantFiled: November 17, 2015Date of Patent: May 24, 2016Assignee: Avalanche Technology, Inc.Inventors: Rajiv Yadav Ranjan, Parviz Keshtbod, Roger Klas Malmhall
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Patent number: 9337413Abstract: One embodiment of the present invention includes a multi-state current-switching magnetic memory element that includes a stack of two or more magnetic tunneling junctions (MTJs), each MTJ having a free layer and being separated from other MTJs in the stack by a seeding layer formed upon an isolation layer. The stack is for storing more than one bit of information, wherein different levels of current applied to the memory element cause switching to different states.Type: GrantFiled: October 29, 2015Date of Patent: May 10, 2016Assignee: Avalanche Technology, Inc.Inventors: Rajiv Yadav Ranjan, Parviz Keshtbod, Roger Klas Malmhall
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Patent number: 9305626Abstract: A magnetic random access memory (MRAM) array having a magnetic tunnel junction (MTJ) to be read using a magnetic state of the MTJ, the MTJ being read by applying a current there through. Further, the MRAM array has a reference MTJ, a sense amplifier coupled to the MTJ and the reference MTJ, the sense amplifier operable to compare the voltage of the MTJ to the reference MTJ in determining the state of the MTJ; a first capacitor coupled to the sense amplifier at a first end and to ground at a second end; and a second capacitor coupled to the sense amplifier at a first end and to ground at a second end, the first capacitor storing the, wherein short voltage pulses are applied to the first end of each of the first and second capacitors when reading the MTJ thereby makes the current flowing through the MTJ there through for small time intervals thereby avoiding read disturbance to the MTJ.Type: GrantFiled: January 16, 2015Date of Patent: April 5, 2016Assignee: Avalanche Technology, Inc.Inventors: Ebrahim Abedifard, Parviz Keshtbod
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Publication number: 20160079517Abstract: The present invention is directed to a multi-state current-switching magnetic memory element configured to store a state by current flowing therethrough to switch the state. The magnetic memory element includes a stack of two or more magnetic tunneling junctions (MTJs) with each MTJ including a free layer with a switchable magnetic orientation perpendicular to a layer plane thereof, a barrier layer, and a fixed layer with a fixed magnetic orientation perpendicular to a layer plane thereof. Each MTJ is separated from other MTJs in the stack by at least an isolation layer. The stack of MTJs may store more than one bit of information. The free layer of each MTJ has a switching current threshold different from free layers of other MTJs in the stack.Type: ApplicationFiled: November 17, 2015Publication date: March 17, 2016Inventors: Rajiv Yadav Ranjan, Parviz Keshtbod, Roger Klas Malmhall
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Publication number: 20160078916Abstract: A method of programming a MTJ includes selecting a MTJ that is coupled to an access transistor at the drain of the access transistor. The gate of the access transistor is coupled to a selected word line (WL), the selected WL is substantially at a first voltage, Vdd; whereas the WLs that are not coupled to the MTJ are left to float. A second voltage, Vx, is applied to the unselected bit lines (BLs) and further applied to a source line (SL), the SL being coupled to the source of the access transistor. A third voltage, Vdd or 0 Volts, is applied to a selected BL, the selected BL is coupled the MTJ. The first voltage is applied to a SL, the SL is coupled to the source of the access transistor thereby causing the WL to boot above the first voltage.Type: ApplicationFiled: April 15, 2014Publication date: March 17, 2016Applicant: Avalanche Technology, Inc.Inventors: Ebrahim ABEDIFARD, Parviz KESHTBOD
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Publication number: 20160064650Abstract: The present invention is directed to a spin-orbitronics device including a magnetic comparison layer structure having a pseudo-invariable magnetization direction; a magnetic free layer structure whose variable magnetization direction can be switched by a switching current passing between the magnetic comparison layer structure and the magnetic free layer structure; an insulating tunnel junction layer interposed between the magnetic comparison layer structure and the magnetic free layer structure; and a non-magnetic transverse polarizing layer formed adjacent to the magnetic comparison layer structure. The pseudo-invariable magnetization direction of the magnetic comparison layer structure may be switched by passing a comparison current through the transverse polarizing layer along a direction that is substantially parallel to a layer plane of the transverse polarizing layer. The pseudo-invariable magnetization direction of the magnetic comparison layer structure is not switched by the switching current.Type: ApplicationFiled: August 20, 2015Publication date: March 3, 2016Inventors: Xiaobin Wang, Parviz Keshtbod, Kimihiro Satoh, Zihui Wang, Huadong Gan
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Publication number: 20160049184Abstract: One embodiment of the present invention includes a multi-state current-switching magnetic memory element includes a stack of two or more magnetic tunneling junctions (MTJs), each MTJ having a free layer and being separated from other MTJs in the stack by a seeding layer formed upon an isolation layer, the stack for storing more than one bit of information, wherein different levels of current applied to the memory element causes switching to different states.Type: ApplicationFiled: October 29, 2015Publication date: February 18, 2016Inventors: Rajiv Yadav Ranjan, Parviz Keshtbod, Roger Klas Malmhall
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Patent number: 9218866Abstract: One embodiment of the present invention includes a multi-state current-switching magnetic memory element includes a stack of two or more magnetic tunneling junctions (MTJs), each MTJ having a free layer and being separated from other MTJs in the stack by a seeding layer formed upon an isolation layer, the stack for storing more than one bit of information, wherein different levels of current applied to the memory element causes switching to different states.Type: GrantFiled: May 13, 2013Date of Patent: December 22, 2015Assignee: AVALANCHE TECHNOLOGY, INC.Inventors: Rajiv Yadav Ranjan, Parviz Keshtbod, Roger Klas Malmhall
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Patent number: 9105343Abstract: The present invention is directed to a method for reading and writing an STT-MRAM multi-level cell (MLC), which includes a plurality of memory elements coupled in series. The method detects the resistance states of individual memory elements in an MLC by sequentially writing at least one of the plurality of memory element to the low resistance state in order of ascending write current threshold. If a written element switches the resistance state thereof after the write step, then the written element was in the high resistance state prior to the write step. Otherwise, the written element was in the low resistance state prior to the write step. The switching of the resistance state can be ascertained by comparing the resistance or voltage values of the plurality of memory elements before and after writing each of the plurality of memory elements in accordance with the embodiments of the present invention.Type: GrantFiled: March 28, 2014Date of Patent: August 11, 2015Assignee: Avalanche Technology, Inc.Inventors: Yuchen Zhou, Bing K Yen, Parviz Keshtbod, Mehdi Asnaashari
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Patent number: 9081669Abstract: A hybrid non-volatile memory device includes a non-volatile random access memory (NVRAM) having an array of magnetic memory elements, the NVRAM being bit-accessible. The hybrid non-volatile device further includes a non-volatile page-mode memory (PMM) made of resistive memory and organized into pages, the non-volatile PMM being page-accessible. Further included in the hybrid non-volatile memory device is a direct memory access (DMA) engine that is coupled to the NVRAM and the non-volatile PMM and transfers data between the NVRAM and the non-volatile PMM during a DMA operation.Type: GrantFiled: April 28, 2014Date of Patent: July 14, 2015Assignee: AVALANCHE TECHNOLOGY, INC.Inventors: Ravishankar Tadepalli, Rajiv Yadav Ranjan, Mehdi Asnaashari, Ngon Van Le, Parviz Keshtbod
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Patent number: 9047968Abstract: A multi-state current-switching magnetic memory element includes a stack of magnetic tunneling junction (MTJ) separated by a non-magnetic layer for storing more than one bit of information, wherein different levels of current applied to the memory element cause switching to different states.Type: GrantFiled: March 14, 2014Date of Patent: June 2, 2015Assignee: AVALANCHE TECHNOLOGY, INC.Inventor: Parviz Keshtbod
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Publication number: 20150146482Abstract: A magnetic random access memory (MRAM) array having a magnetic tunnel junction (MTJ) to be read using a magnetic state of the MTJ, the MTJ being read by applying a current there through. Further, the MRAM array has a reference MTJ, a sense amplifier coupled to the MTJ and the reference MTJ, the sense amplifier operable to compare the voltage of the MTJ to the reference MTJ in determining the state of the MTJ; a first capacitor coupled to the sense amplifier at a first end and to ground at a second end; and a second capacitor coupled to the sense amplifier at a first end and to ground at a second end, the first capacitor storing the, wherein short voltage pulses are applied to the first end of each of the first and second capacitors when reading the MTJ thereby makes the current flowing through the MTJ there through for small time intervals thereby avoiding read disturbance to the MTJ.Type: ApplicationFiled: January 16, 2015Publication date: May 28, 2015Inventors: Ebrahim Abedifard, Parviz Keshtbod
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Publication number: 20150131370Abstract: The present invention is directed to a method for reading and writing an STT-MRAM multi-level cell (MLC), which includes a plurality of memory elements coupled in series. The method detects the resistance states of individual memory elements in an MLC by sequentially writing at least one of the plurality of memory element to the low resistance state in order of ascending write current threshold. If a written element switches the resistance state thereof after the write step, then the written element was in the high resistance state prior to the write step. Otherwise, the written element was in the low resistance state prior to the write step. The switching of the resistance state can be ascertained by comparing the resistance or voltage values of the plurality of memory elements before and after writing each of the plurality of memory elements in accordance with the embodiments of the present invention.Type: ApplicationFiled: March 28, 2014Publication date: May 14, 2015Applicant: Avalanche Technology Inc.Inventors: Yuchen Zhou, Bing K. Yen, Parviz Keshtbod, Mehdi Asnaashari
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Publication number: 20150131369Abstract: A method of programming a voltage-controlled magnetoresistive tunnel junction (MTJ) includes applying a programming voltage pulse (Vp), reading the voltage-controlled MTJ, and determining if the voltage-controlled MTJ is programmed to a desired state and if not, changing the Vp and repeating the applying and reading steps until the voltage-controlled MTJ is programmed to the desired state.Type: ApplicationFiled: March 14, 2014Publication date: May 14, 2015Applicant: Avalanche Technology, Inc.Inventors: Ebrahim ABEDIFARD, Parviz KESHTBOD
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Patent number: 8980649Abstract: In accordance with a method of the present invention, a method of manufacturing a magnetic random access memory (MRAM) cell and a corresponding structure thereof are disclosed to include a multi-stage manufacturing process. The multi-stage manufacturing process includes performing a front end on-line (FEOL) stage to manufacture logic and non-magnetic portions of the memory cell by forming an intermediate interlayer dielectric (ILD) layer, forming intermediate metal pillars embedded in the intermediate ILD layer, depositing a conductive metal cap on top of the intermediate ILD layer and the metal pillars, performing magnetic fabrication stage to make a magnetic material portion of the memory cell being manufactured, and performing back end on-line (BEOL) stage to make metal and contacts of the memory cell being manufactured.Type: GrantFiled: September 16, 2013Date of Patent: March 17, 2015Assignee: Avalanche Technology, Inc.Inventors: Rajiv Yadav Ranjan, Parviz Keshtbod, Roger Klas Malmhall