Abstract: A system and method for adding hierarchy to a netlist. A netlist is received and converted into a connected graph. Location parameters for the nodes of the connected graph are mapped onto the connected graph. Landmark structures are identified in the connected graph, wherein identifying includes recording a location associated with each landmark structure. Patterns are searched for in the connected graph, wherein searching proceeds outward from an anchor defined by the location of each of the identified landmark structures.

Abstract: A system and method for adding hierarchy to a netlist. A netlist is received and converted into a connected graph. Location parameters for the nodes of the connected graph are mapped onto the connected graph. Landmark structures are identified in the connected graph, wherein identifying includes recording a location associated with each landmark structure. Patterns are searched for in the connected graph, wherein searching proceeds outward from an anchor defined by the location of each of the identified landmark structures.

Abstract: A system and method for reverse synthesizing an integrated circuit from a netlist. A netlist extracted from a device under review is received and converted to a connected graph. Blocks of cells are identified within the connected graph and a circuit model is formed from the blocks of cells, wherein forming includes iteratively building more complex blocks of cells from simpler blocks of cells.

Abstract: A system and method for reverse synthesizing an integrated circuit from a netlist. A netlist extracted from a device under review is received and converted to a connected graph. Blocks of cells are identified within the connected graph and a circuit model is formed from the blocks of cells, wherein forming includes iteratively building more complex blocks of cells from simpler blocks of cells.

Abstract: A method and method of extracting information from a netlist. The netlist for a device under test (DUT) is read and a circuit selected to be transformed. Transformation candidates are identified using transformation specific criteria and verification methods are applied to prove the transformation is equivalent to the circuit being transformed. If the candidate transformation is equivalent to the circuit being transformed, the system commits to the transformation. If the candidate transformation is not equivalent to the circuit being transformed, the transformation is undone.

Abstract: A method of testing an electrical circuit includes applying test vectors to a circuit, detecting thermal changes in portions of the circuit during application of the test vectors, and identifying unexpected activity corresponding to the thermal changes. The method supplements standard testing techniques to provide a new method of assessing operation of fabricated integrated circuits and programmed field programmable gate arrays.

Abstract: A method of testing an electrical circuit includes applying test vectors to a circuit, detecting thermal changes in portions of the circuit during application of the test vectors, and identifying unexpected activity corresponding to the thermal changes. The method supplements standard testing techniques to provide a new method of assessing operation of fabricated integrated circuits and programmed field programmable gate arrays.