Patents by Inventor Pascal Besson
Pascal Besson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11380543Abstract: A substrate is provided with a monocrystalline silicon-germanium layer with a first surface covered by a protective oxide obtained by wet process and having a degradation temperature. The protective oxide is transformed into fluorinated salt which is then eliminated. The substrate is placed in a processing chamber at a lower temperature than the degradation temperature and is subjected to a temperature ramp up to a higher temperature than the degradation temperature. The first surface is annealed in a hydrogen atmosphere devoid of silicon, germanium and precursors of the materials forming the target layer. When the temperature ramp is applied, a silicon precursor is inserted in the processing chamber between a loading temperature and the degradation temperature to deposit a monocrystalline buffer layer. A mono-crystalline target layer is deposited by chemical vapour deposition.Type: GrantFiled: December 17, 2019Date of Patent: July 5, 2022Assignees: COMMISSARIAT À L'ÉNERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, UNIVERSITÉ GRENOBLE ALPES, CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUEInventors: Pierre-Edouard Raynal, Pascal Besson, Jean-Michel Hartmann, Virginie Loup, Laurent Vallier
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Publication number: 20220037157Abstract: The present description concerns a method of manufacturing a first wafer, intended to be assembled to a second wafer by molecular bonding, including the successive steps of: forming a stack of layers at the surface of a substrate; and successive chemical etchings of the edges of said layers from the layer of the stack most distant from the substrate, across a smaller and smaller width.Type: ApplicationFiled: July 23, 2021Publication date: February 3, 2022Applicant: STMICROELECTRONICS SAInventors: Francois GUYADER, Pascal BESSON
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Publication number: 20200194259Abstract: A substrate is provided with a monocrystalline silicon-germanium layer with a first surface covered by a protective oxide obtained by wet process and having a degradation temperature. The protective oxide is transformed into fluorinated salt which is then eliminated. The substrate is placed in a processing chamber at a lower temperature than the degradation temperature and is subjected to a temperature ramp up to a higher temperature than the degradation temperature. The first surface is annealed in a hydrogen atmosphere devoid of silicon, germanium and precursors of the materials forming the target layer. When the temperature ramp is applied, a silicon precursor is inserted in the processing chamber between a loading temperature and the degradation temperature to deposit a monocrystalline buffer layer. A mono-crystalline target layer is deposited by chemical vapour deposition.Type: ApplicationFiled: December 17, 2019Publication date: June 18, 2020Applicants: COMMISSARIAT À L'ÉNERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, UNIVERSITÉ GRENOBLE ALPES, CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUEInventors: Pierre-Edouard RAYNAL, Pascal BESSON, Jean-Michel HARTMANN, Virginie LOUP, Laurent VALLIER
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Patent number: 9831095Abstract: A method for performing selective etching of a semiconductor material in solution having the following successive steps: a) providing a substrate having a layer of amorphous semiconductor material to be etched and a layer of crystalline semiconductor material; b) oxidizing the surfaces of the layers of amorphous semiconductor material and of crystalline semiconductor material so as to form a first protective layer at the surface of the amorphous semiconductor material and a second protective layer at the surface of the crystalline semiconductor material; c) etching the first protective layer and the layer of amorphous semiconductor material with an alkaline etching solution, the etch rate v1 of the first protective layer being higher than the etch rate v2 of the second protective layer.Type: GrantFiled: November 25, 2016Date of Patent: November 28, 2017Assignee: COMMISSARIAT À L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVESInventors: Virginie Loup, Pascal Besson
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Publication number: 20170148638Abstract: A method for performing selective etching of a semiconductor material in solution having the following successive steps: a) providing a substrate having a layer of amorphous semiconductor material to be etched and a layer of crystalline semiconductor material; b) oxidizing the surfaces of the layers of amorphous semiconductor material and of crystalline semiconductor material so as to form a first protective layer at the surface of the amorphous semiconductor material and a second protective layer at the surface of the crystalline semiconductor material; c) etching the first protective layer and the layer of amorphous semiconductor material with an alkaline etching solution, the etch rate v1 of the first protective layer being higher than the etch rate v2 of the second protective layer.Type: ApplicationFiled: November 25, 2016Publication date: May 25, 2017Applicant: COMMISSARIAT À L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVESInventors: Virginie LOUP, Pascal BESSON
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Patent number: 8759174Abstract: A method of fabricating a device, including the steps of forming a first silicon oxide layer within a first region of the device and a second silicon oxide layer within a second region of the device, implanting doping ions of a first type into the first region, implanting doping ions of a second type into the second region, and etching the first and second regions for a determined duration such that the first silicon oxide layer is removed and at least a part of the second silicon oxide layer remains.Type: GrantFiled: September 15, 2009Date of Patent: June 24, 2014Assignees: STMicroelectronics (Crolles 2) SAS, STMicroelectronics S.A., NXP B.V.Inventors: Markus Müller, Alexandre Mondot, Pascal Besson
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Patent number: 8524522Abstract: A process for producing a microelectronic device includes producing a first semiconductor substrate which includes a first layer and a second layer present between a first side and a second side of the substrate. First electronic components and an interconnecting part are produced on and above the second side. The substrate is then thinned by a first selective etch applied from the first side and stopping on the first layer followed by a second selective etch stopping on the second layer. A second substrate is attached over the interconnecting part. The electronic components may comprise optoelectronic devices which are illuminated through the second layer.Type: GrantFiled: December 9, 2010Date of Patent: September 3, 2013Assignees: STMicroelectronics S.A., STMicroelectronics (Crolles 2) SASInventors: Michel Marty, Didier Dutartre, Francois Roy, Pascal Besson, Jens Prima
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Publication number: 20110140220Abstract: A process for producing a microelectronic device includes producing a first semiconductor substrate which includes a first layer and a second layer present between a first side and a second side of the substrate. First electronic components and an interconnecting part are produced on and above the second side. The substrate is then thinned by a first selective etch applied from the first side and stopping on the first layer followed by a second selective etch stopping on the second layer. A second substrate is attached over the interconnecting part. The electronic components may comprise optoelectronic devices which are illuminated through the second layer.Type: ApplicationFiled: December 9, 2010Publication date: June 16, 2011Applicants: STMicroelectronics S.A., STMicroelectronics (Crolles2) SASInventors: Michel Marty, Didier Dutartre, Francois Roy, Pascal Besson, Jens Prima
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Publication number: 20100041189Abstract: A method of fabricating a device, including the steps of forming a first silicon oxide layer within a first region of the device and a second silicon oxide layer within a second region of the device, implanting doping ions of a first type into the first region, implanting doping ions of a second type into the second region, and etching the first and second regions for a determined duration such that the first silicon oxide layer is removed and at least a part of the second silicon oxide layer remains.Type: ApplicationFiled: September 15, 2009Publication date: February 18, 2010Applicants: STMicroelectronics (Crolles) 2 SAS, STMicroelectronics S.A., NXP B.V.Inventors: Markus Müller, Alexandre Mondot, Pascal Besson
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Patent number: 7641738Abstract: A method of wet cleaning a surface is disclosed. The method of wet cleaning a surface of at least one material chosen from silicon, silicon-germanium alloys, A(III)/B(V)-type semiconductors and epitaxially grown crystalline materials, such as germanium, includes the following successive steps: a) the surface is brought into contact with an HF solution; b) the surface is rinsed with acidified, deionized water, then a powerful oxidizing agent is added to the deionized water and the rinsing is continued; c) optionally, step a) is repeated, once or twice, while optionally reducing the contacting time; d) step b) is optionally repeated, once or twice; and e) the surface is dried.Type: GrantFiled: July 6, 2007Date of Patent: January 5, 2010Assignee: Commissariat a l'Energie AtomiqueInventors: Alexandra Abbadie, Pascal Besson, Marie-Noëlle Semeria
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Patent number: 7491644Abstract: A process for fabricating a transistor that includes a gate located in the immediate proximity of a dielectric includes a step of etching a layer of gate material. The gate etching step includes plasma etching of the gate layer over the major portion of its thickness so as to laterally define the gate and chemical etching of a residual portion of the gate layer so as to define the gate as far as the dielectric.Type: GrantFiled: September 9, 2005Date of Patent: February 17, 2009Assignees: Commissariat a l'Energie Atomique, ST Microelectronics SAInventors: Maud Vinet, Pascal Besson, Bernard Previtali, Christian Vizioz
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Publication number: 20070256705Abstract: Method of wet cleaning a surface of at least one material chosen from silicon, silicon-germanium alloys, A(III)/B(V)-type semiconductors and epitaxially grown crystalline materials, such as germanium, in which method the following successive steps are carried out: a) the surface is brought into contact with an HF solution; b) the surface is rinsed with acidified, deionized water, then a powerful oxidizing agent is added to the deionized water and the rinsing is continued; c) optionally, step a) is repeated, once or twice, while optionally reducing the contacting time; d) step b) is optionally repeated, once or twice; and e) the surface is dried. Process for fabricating an electronic, optical or optoelectronic device, such as a CMOS or MOSFET device, comprising at least one wet cleaning step using the said cleaning method.Type: ApplicationFiled: July 6, 2007Publication date: November 8, 2007Inventors: Alexandra Abbadie, Pascal Besson, Marie-Noelle Semeria
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Patent number: 7250085Abstract: Method of wet cleaning a surface of at least one material chosen from silicon, silicon-germanium alloys, A(III)/B(V)-type semiconductors and epitaxially grown crystalline materials, such as germanium, in which method the following successive steps are carried out: a) the surface is brought into contact with an HF solution; b) the surface is rinsed with acidified, deionized water, then a powerful oxidizing agent is added to the deionized water and the rinsing is continued; c) optionally, step a) is repeated, once or twice, while optionally reducing the contacting time; d) step b) is optionally repeated, once or twice; and e) the surface is dried. Process for fabricating an electronic, optical or optoelectronic device, such as a CMOS or MOSFET device, comprising at least one wet cleaning step using the said cleaning method.Type: GrantFiled: December 29, 2004Date of Patent: July 31, 2007Assignee: Commissariat A l'Energie AtomiqueInventors: Alexandra Abbadie, Pascal Besson, Marie-Noëlle Semeria
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Publication number: 20070173064Abstract: A process for fabricating a transistor comprising a gate (50?) located in the immediate proximity of a dielectric (46) includes a step of etching a layer of gate material. This gate etching step comprises the following steps: plasma etching of this layer over the major portion of its thickness so as to laterally define the gate (50?); chemical etching of a residual portion (48?) of this layer so as to define this gate as far as the dielectric (46).Type: ApplicationFiled: September 9, 2005Publication date: July 26, 2007Inventors: Maud Vinet, Pascal Besson, Bernard Previtali, Christian Vizioz
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Publication number: 20070042687Abstract: In a chemical-mechanical polishing machine, polishing product comprising abrasive particles suspended in a reactive liquid is fed to the machine for use in a polishing operation that is divided into at least a first step and a second step. During the second step, the polishing machine is fed via a filter with a product containing fewer large particles than the product feeding the polishing machine during the first step. The feed device may be formed of two parallel lines which are provided with valves. At least one of those lines is provided with the filter.Type: ApplicationFiled: July 5, 2006Publication date: February 22, 2007Applicant: STMicroelectronics (Crolles 2) SASInventors: Sebastien Petitdidier, Pascal Besson
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Publication number: 20050139231Abstract: Method of wet cleaning a surface of at least one material chosen from silicon, silicon-germanium alloys, A(III)/B(V)-type semiconductors and epitaxially grown crystalline materials, such as germanium, in which method the following successive steps are carried out: a) the surface is brought into contact with an HF solution; b) the surface is rinsed with acidified, deionized water, then a powerful oxidizing agent is added to the deionized water and the rinsing is continued; c) optionally, step a) is repeated, once or twice, while optionally reducing the contacting time; d) step b) is optionally repeated, once or twice; and e) the surface is dried. Process for fabricating an electronic, optical or optoelectronic device, such as a CMOS or MOSFET device, comprising at least one wet cleaning step using the said cleaning method.Type: ApplicationFiled: December 29, 2004Publication date: June 30, 2005Inventors: Alexandra Abadie, Pascal Besson, Marie-Noelle Semeria