Patents by Inventor Pascal Besson

Pascal Besson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11380543
    Abstract: A substrate is provided with a monocrystalline silicon-germanium layer with a first surface covered by a protective oxide obtained by wet process and having a degradation temperature. The protective oxide is transformed into fluorinated salt which is then eliminated. The substrate is placed in a processing chamber at a lower temperature than the degradation temperature and is subjected to a temperature ramp up to a higher temperature than the degradation temperature. The first surface is annealed in a hydrogen atmosphere devoid of silicon, germanium and precursors of the materials forming the target layer. When the temperature ramp is applied, a silicon precursor is inserted in the processing chamber between a loading temperature and the degradation temperature to deposit a monocrystalline buffer layer. A mono-crystalline target layer is deposited by chemical vapour deposition.
    Type: Grant
    Filed: December 17, 2019
    Date of Patent: July 5, 2022
    Assignees: COMMISSARIAT À L'ÉNERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, UNIVERSITÉ GRENOBLE ALPES, CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE
    Inventors: Pierre-Edouard Raynal, Pascal Besson, Jean-Michel Hartmann, Virginie Loup, Laurent Vallier
  • Publication number: 20220037157
    Abstract: The present description concerns a method of manufacturing a first wafer, intended to be assembled to a second wafer by molecular bonding, including the successive steps of: forming a stack of layers at the surface of a substrate; and successive chemical etchings of the edges of said layers from the layer of the stack most distant from the substrate, across a smaller and smaller width.
    Type: Application
    Filed: July 23, 2021
    Publication date: February 3, 2022
    Applicant: STMICROELECTRONICS SA
    Inventors: Francois GUYADER, Pascal BESSON
  • Publication number: 20200194259
    Abstract: A substrate is provided with a monocrystalline silicon-germanium layer with a first surface covered by a protective oxide obtained by wet process and having a degradation temperature. The protective oxide is transformed into fluorinated salt which is then eliminated. The substrate is placed in a processing chamber at a lower temperature than the degradation temperature and is subjected to a temperature ramp up to a higher temperature than the degradation temperature. The first surface is annealed in a hydrogen atmosphere devoid of silicon, germanium and precursors of the materials forming the target layer. When the temperature ramp is applied, a silicon precursor is inserted in the processing chamber between a loading temperature and the degradation temperature to deposit a monocrystalline buffer layer. A mono-crystalline target layer is deposited by chemical vapour deposition.
    Type: Application
    Filed: December 17, 2019
    Publication date: June 18, 2020
    Applicants: COMMISSARIAT À L'ÉNERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, UNIVERSITÉ GRENOBLE ALPES, CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE
    Inventors: Pierre-Edouard RAYNAL, Pascal BESSON, Jean-Michel HARTMANN, Virginie LOUP, Laurent VALLIER
  • Patent number: 9831095
    Abstract: A method for performing selective etching of a semiconductor material in solution having the following successive steps: a) providing a substrate having a layer of amorphous semiconductor material to be etched and a layer of crystalline semiconductor material; b) oxidizing the surfaces of the layers of amorphous semiconductor material and of crystalline semiconductor material so as to form a first protective layer at the surface of the amorphous semiconductor material and a second protective layer at the surface of the crystalline semiconductor material; c) etching the first protective layer and the layer of amorphous semiconductor material with an alkaline etching solution, the etch rate v1 of the first protective layer being higher than the etch rate v2 of the second protective layer.
    Type: Grant
    Filed: November 25, 2016
    Date of Patent: November 28, 2017
    Assignee: COMMISSARIAT À L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Virginie Loup, Pascal Besson
  • Publication number: 20170148638
    Abstract: A method for performing selective etching of a semiconductor material in solution having the following successive steps: a) providing a substrate having a layer of amorphous semiconductor material to be etched and a layer of crystalline semiconductor material; b) oxidizing the surfaces of the layers of amorphous semiconductor material and of crystalline semiconductor material so as to form a first protective layer at the surface of the amorphous semiconductor material and a second protective layer at the surface of the crystalline semiconductor material; c) etching the first protective layer and the layer of amorphous semiconductor material with an alkaline etching solution, the etch rate v1 of the first protective layer being higher than the etch rate v2 of the second protective layer.
    Type: Application
    Filed: November 25, 2016
    Publication date: May 25, 2017
    Applicant: COMMISSARIAT À L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Virginie LOUP, Pascal BESSON
  • Patent number: 8759174
    Abstract: A method of fabricating a device, including the steps of forming a first silicon oxide layer within a first region of the device and a second silicon oxide layer within a second region of the device, implanting doping ions of a first type into the first region, implanting doping ions of a second type into the second region, and etching the first and second regions for a determined duration such that the first silicon oxide layer is removed and at least a part of the second silicon oxide layer remains.
    Type: Grant
    Filed: September 15, 2009
    Date of Patent: June 24, 2014
    Assignees: STMicroelectronics (Crolles 2) SAS, STMicroelectronics S.A., NXP B.V.
    Inventors: Markus Müller, Alexandre Mondot, Pascal Besson
  • Patent number: 8524522
    Abstract: A process for producing a microelectronic device includes producing a first semiconductor substrate which includes a first layer and a second layer present between a first side and a second side of the substrate. First electronic components and an interconnecting part are produced on and above the second side. The substrate is then thinned by a first selective etch applied from the first side and stopping on the first layer followed by a second selective etch stopping on the second layer. A second substrate is attached over the interconnecting part. The electronic components may comprise optoelectronic devices which are illuminated through the second layer.
    Type: Grant
    Filed: December 9, 2010
    Date of Patent: September 3, 2013
    Assignees: STMicroelectronics S.A., STMicroelectronics (Crolles 2) SAS
    Inventors: Michel Marty, Didier Dutartre, Francois Roy, Pascal Besson, Jens Prima
  • Publication number: 20110140220
    Abstract: A process for producing a microelectronic device includes producing a first semiconductor substrate which includes a first layer and a second layer present between a first side and a second side of the substrate. First electronic components and an interconnecting part are produced on and above the second side. The substrate is then thinned by a first selective etch applied from the first side and stopping on the first layer followed by a second selective etch stopping on the second layer. A second substrate is attached over the interconnecting part. The electronic components may comprise optoelectronic devices which are illuminated through the second layer.
    Type: Application
    Filed: December 9, 2010
    Publication date: June 16, 2011
    Applicants: STMicroelectronics S.A., STMicroelectronics (Crolles2) SAS
    Inventors: Michel Marty, Didier Dutartre, Francois Roy, Pascal Besson, Jens Prima
  • Publication number: 20100041189
    Abstract: A method of fabricating a device, including the steps of forming a first silicon oxide layer within a first region of the device and a second silicon oxide layer within a second region of the device, implanting doping ions of a first type into the first region, implanting doping ions of a second type into the second region, and etching the first and second regions for a determined duration such that the first silicon oxide layer is removed and at least a part of the second silicon oxide layer remains.
    Type: Application
    Filed: September 15, 2009
    Publication date: February 18, 2010
    Applicants: STMicroelectronics (Crolles) 2 SAS, STMicroelectronics S.A., NXP B.V.
    Inventors: Markus Müller, Alexandre Mondot, Pascal Besson
  • Patent number: 7641738
    Abstract: A method of wet cleaning a surface is disclosed. The method of wet cleaning a surface of at least one material chosen from silicon, silicon-germanium alloys, A(III)/B(V)-type semiconductors and epitaxially grown crystalline materials, such as germanium, includes the following successive steps: a) the surface is brought into contact with an HF solution; b) the surface is rinsed with acidified, deionized water, then a powerful oxidizing agent is added to the deionized water and the rinsing is continued; c) optionally, step a) is repeated, once or twice, while optionally reducing the contacting time; d) step b) is optionally repeated, once or twice; and e) the surface is dried.
    Type: Grant
    Filed: July 6, 2007
    Date of Patent: January 5, 2010
    Assignee: Commissariat a l'Energie Atomique
    Inventors: Alexandra Abbadie, Pascal Besson, Marie-Noëlle Semeria
  • Patent number: 7491644
    Abstract: A process for fabricating a transistor that includes a gate located in the immediate proximity of a dielectric includes a step of etching a layer of gate material. The gate etching step includes plasma etching of the gate layer over the major portion of its thickness so as to laterally define the gate and chemical etching of a residual portion of the gate layer so as to define the gate as far as the dielectric.
    Type: Grant
    Filed: September 9, 2005
    Date of Patent: February 17, 2009
    Assignees: Commissariat a l'Energie Atomique, ST Microelectronics SA
    Inventors: Maud Vinet, Pascal Besson, Bernard Previtali, Christian Vizioz
  • Publication number: 20070256705
    Abstract: Method of wet cleaning a surface of at least one material chosen from silicon, silicon-germanium alloys, A(III)/B(V)-type semiconductors and epitaxially grown crystalline materials, such as germanium, in which method the following successive steps are carried out: a) the surface is brought into contact with an HF solution; b) the surface is rinsed with acidified, deionized water, then a powerful oxidizing agent is added to the deionized water and the rinsing is continued; c) optionally, step a) is repeated, once or twice, while optionally reducing the contacting time; d) step b) is optionally repeated, once or twice; and e) the surface is dried. Process for fabricating an electronic, optical or optoelectronic device, such as a CMOS or MOSFET device, comprising at least one wet cleaning step using the said cleaning method.
    Type: Application
    Filed: July 6, 2007
    Publication date: November 8, 2007
    Inventors: Alexandra Abbadie, Pascal Besson, Marie-Noelle Semeria
  • Patent number: 7250085
    Abstract: Method of wet cleaning a surface of at least one material chosen from silicon, silicon-germanium alloys, A(III)/B(V)-type semiconductors and epitaxially grown crystalline materials, such as germanium, in which method the following successive steps are carried out: a) the surface is brought into contact with an HF solution; b) the surface is rinsed with acidified, deionized water, then a powerful oxidizing agent is added to the deionized water and the rinsing is continued; c) optionally, step a) is repeated, once or twice, while optionally reducing the contacting time; d) step b) is optionally repeated, once or twice; and e) the surface is dried. Process for fabricating an electronic, optical or optoelectronic device, such as a CMOS or MOSFET device, comprising at least one wet cleaning step using the said cleaning method.
    Type: Grant
    Filed: December 29, 2004
    Date of Patent: July 31, 2007
    Assignee: Commissariat A l'Energie Atomique
    Inventors: Alexandra Abbadie, Pascal Besson, Marie-Noëlle Semeria
  • Publication number: 20070173064
    Abstract: A process for fabricating a transistor comprising a gate (50?) located in the immediate proximity of a dielectric (46) includes a step of etching a layer of gate material. This gate etching step comprises the following steps: plasma etching of this layer over the major portion of its thickness so as to laterally define the gate (50?); chemical etching of a residual portion (48?) of this layer so as to define this gate as far as the dielectric (46).
    Type: Application
    Filed: September 9, 2005
    Publication date: July 26, 2007
    Inventors: Maud Vinet, Pascal Besson, Bernard Previtali, Christian Vizioz
  • Publication number: 20070042687
    Abstract: In a chemical-mechanical polishing machine, polishing product comprising abrasive particles suspended in a reactive liquid is fed to the machine for use in a polishing operation that is divided into at least a first step and a second step. During the second step, the polishing machine is fed via a filter with a product containing fewer large particles than the product feeding the polishing machine during the first step. The feed device may be formed of two parallel lines which are provided with valves. At least one of those lines is provided with the filter.
    Type: Application
    Filed: July 5, 2006
    Publication date: February 22, 2007
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Sebastien Petitdidier, Pascal Besson
  • Publication number: 20050139231
    Abstract: Method of wet cleaning a surface of at least one material chosen from silicon, silicon-germanium alloys, A(III)/B(V)-type semiconductors and epitaxially grown crystalline materials, such as germanium, in which method the following successive steps are carried out: a) the surface is brought into contact with an HF solution; b) the surface is rinsed with acidified, deionized water, then a powerful oxidizing agent is added to the deionized water and the rinsing is continued; c) optionally, step a) is repeated, once or twice, while optionally reducing the contacting time; d) step b) is optionally repeated, once or twice; and e) the surface is dried. Process for fabricating an electronic, optical or optoelectronic device, such as a CMOS or MOSFET device, comprising at least one wet cleaning step using the said cleaning method.
    Type: Application
    Filed: December 29, 2004
    Publication date: June 30, 2005
    Inventors: Alexandra Abadie, Pascal Besson, Marie-Noelle Semeria