Patents by Inventor Pascal Bierbaumer

Pascal Bierbaumer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12660601
    Abstract: A semiconductor die includes: a semiconductor substrate having an active region and an edge termination region that separates the active region from an edge of the semiconductor substrate; a plurality of transistor cells formed in the active region; a structured power metallization above the semiconductor substrate and including a gate pad and a gate runner that extends from the gate pad along one or more but not all sides of the semiconductor die above the edge termination region, the gate runner electrically connecting the gate pad to gate electrodes of the transistor cells; and a tungsten runner that follows the gate runner and contacts an underside of the gate runner. The tungsten runner is present above the edge termination region along each side of the semiconductor die that is at least partly devoid of the gate runner. A Method of producing the semiconductor die is also described.
    Type: Grant
    Filed: July 22, 2022
    Date of Patent: June 16, 2026
    Assignee: Infineon Technologies Austria AG
    Inventors: Ingmar Neumann, Adrian Finney, Pascal Bierbaumer, Laszlo Juhasz
  • Publication number: 20240030137
    Abstract: A semiconductor die includes: a semiconductor substrate having an active region and an edge termination region that separates the active region from an edge of the semiconductor substrate; a plurality of transistor cells formed in the active region; a structured power metallization above the semiconductor substrate and including a gate pad and a gate runner that extends from the gate pad along one or more but not all sides of the semiconductor die above the edge termination region, the gate runner electrically connecting the gate pad to gate electrodes of the transistor cells; and a tungsten runner that follows the gate runner and contacts an underside of the gate runner. The tungsten runner is present above the edge termination region along each side of the semiconductor die that is at least partly devoid of the gate runner. A Method of producing the semiconductor die is also described.
    Type: Application
    Filed: July 22, 2022
    Publication date: January 25, 2024
    Inventors: Ingmar Neumann, Adrian Finney, Pascal Bierbaumer, Laszlo Juhasz