Patents by Inventor Pascal CAUNEGRE

Pascal CAUNEGRE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9922146
    Abstract: An integrated circuit design tool apparatus includes a processing resource configured to support a circuit simulator, a circuit sensitivity optimizer and a circuit sensitivity calculator. The circuit sensitivity optimizer is adapted to communicate to the circuit simulator a first dynamic list of selected devices of the circuit; and a second dynamic list of selected process parameters associated with the selected devices of the first dynamic list. The circuit simulator is configured to communicate to the circuit sensitivity calculator, a performance metrics of the circuit in response thereto. The circuit sensitivity calculator is configured to determine one sensitivity coefficient for each device of the first dynamic list in response thereto. The circuit sensitivity calculator is further configured to determine and communicate to the circuit sensitivity optimizer a variance of the performance metrics and also adapted to gradually determine whether or not to further communicate with the circuit simulator.
    Type: Grant
    Filed: March 21, 2013
    Date of Patent: March 20, 2018
    Assignee: NXP USA, Inc.
    Inventor: Pascal Caunegre
  • Patent number: 9424379
    Abstract: A simulation system for testing a simulation of a device against one or more violation rules is described. The simulation system comprises a device simulator for executing the simulation of a device using a device design, a device model and a simulation scenario; and one or more violation monitors, one for each violation rule. Each violation monitor comprises a violation information detector for detecting one or more violations of the respective violation rule during the executing of the simulation and, for each violation, determining information representing the respective violation; a violation score unit for calculating, for each violation of the respective violation rule, a violation score in dependence on the information representing the violation and on a violation rule-specific scheme, and a rule score unit for determining, for the respective violation rule, a rule score from the violation scores of the one or more violations during the simulation.
    Type: Grant
    Filed: May 31, 2012
    Date of Patent: August 23, 2016
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Xavier Hours, Pascal Caunegre, Christophe Oger, Mehul Shroff
  • Publication number: 20160063149
    Abstract: An integrated circuit design tool apparatus includes a processing resource configured to support a circuit simulator, a circuit sensitivity optimiser and a circuit sensitivity calculator. The circuit sensitivity optimiser is adapted to communicate to the circuit simulator a first dynamic list of selected devices of the circuit; and a second dynamic list of selected process parameters associated with the selected devices of the first dynamic list. The circuit simulator is configured to communicate to the circuit sensitivity calculator, a performance metrics of the circuit in response thereto. The circuit sensitivity calculator is configured to determine one sensitivity coefficient for each device of the first dynamic list in response thereto. The circuit sensitivity calculator is further configured to determine and communicate to the circuit sensitivity optimiser a variance of the performance metrics and also adapted to gradually determine whether or not to further communicate with the circuit simulator.
    Type: Application
    Filed: March 21, 2013
    Publication date: March 3, 2016
    Applicant: Freescale Semiconductor, Inc.
    Inventor: PASCAL CAUNEGRE
  • Publication number: 20150121325
    Abstract: A simulation system for testing a simulation of a device against one or more violation rules is described. The simulation system comprises a device simulator for executing the simulation of a device using a device design, a device model and a simulation scenario; and one or more violation monitors, one for each violation rule. Each violation monitor comprises a violation information detector for detecting one or more violations of the respective violation rule during the executing of the simulation and, for each violation, determining information representing the respective violation; a violation score unit for calculating, for each violation of the respective violation rule, a violation score in dependence on the information representing the violation and on a violation rule-specific scheme, and a rule score unit for determining, for the respective violation rule, a rule score from the violation scores of the one or more violations during the simulation.
    Type: Application
    Filed: May 31, 2012
    Publication date: April 30, 2015
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Xavier Hours, Pascal Caunegre, Christophe Oger, Mehul Shroff
  • Patent number: 8589856
    Abstract: An integrated circuit design tool apparatus including a processing resource arranged to support a circuit simulator, a circuit simulator interrogator, and a well distance calculator is provided. The circuit simulator interrogator communicates first and second well distance values separately to the circuit simulator and receives first and second performance parameter value back from the circuit simulator interrogator in response. The well distance calculator determines a performance parameter limit value, and projects, substantially linearly, a well distance change value in respect of the performance parameter limit value using the first and second performance parameter values, the performance parameter limit value and a trial well distance change value. Also, a well distance change characterizing equation using the well distance change value projected is used in order to obtain the minimum well distance value associated with the performance parameter limit value.
    Type: Grant
    Filed: February 16, 2010
    Date of Patent: November 19, 2013
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Pascal Caunegre
  • Publication number: 20120317532
    Abstract: An integrated circuit design tool apparatus including a processing resource arranged to support a circuit simulator, a circuit simulator interrogator, and a well distance calculator is provided. The circuit simulator interrogator communicates first and second well distance values separately to the circuit simulator and receives first and second performance parameter value back from the circuit simulator interrogator in response. The well distance calculator determines a performance parameter limit value, and projects, substantially linearly, a well distance change value in respect of the performance parameter limit value using the first and second performance parameter values, the performance parameter limit value and a trial well distance change value. Also, a well distance change characterising equation using the well distance change value projected is used in order to obtain the minimum well distance value associated with the performance parameter limit value.
    Type: Application
    Filed: February 16, 2010
    Publication date: December 13, 2012
    Applicant: Freescale Semiconductor, Inc.
    Inventor: Pascal CAUNEGRE