Abstract: Method for producing at least one via (200) in the thickness of a substrate and an electrically conducting line (280) connected to the via (200) and formed on a face (220) of the substrate, comprising: forming, from the face (220), a via cavity comprising a side wall and a bottom; forming an isolating layer (240) on the side wall and the bottom of the cavity; forming at least one line pattern on the face (220) of the substrate, with the line pattern opening into the via cavity; filling with an electrically conducting material the line pattern and the via cavity, a filling so configured as not to totally fill said cavity; Forming at least one line pattern comprises, after forming the isolating layer (240), the forming of a trench (244) in a portion of the isolating layer (240) positioned on the face (220).

Abstract: A method for determining, in a first semiconductor material wafer having at least one through via, mechanical stress induced by the at least one through via, this method including the steps of: manufacturing a test structure from a second wafer of the same nature as the first wafer, in which the at least one through via is formed by a substantially identical method, a rear surface layer being further arranged on this second wafer so that the via emerges on the layer; measuring the mechanical stress in the rear surface layer; and deducing therefrom the mechanical stress induced in the first semiconductor material wafer.

Abstract: Method for producing at least one via (200) in the thickness of a substrate and an electrically conducting line (280) connected to the via (200) and formed on a face (220) of the substrate, comprising: forming, from the face (220), a via cavity comprising a side wall and a bottom; forming an isolating layer (240) on the side wall and the bottom of the cavity; forming at least one line pattern on the face (220) of the substrate, with the line pattern opening into the via cavity; filling with an electrically conducting material the line pattern and the via cavity, a filling so configured as not to totally fill said cavity; Forming at least one line pattern comprises, after forming the isolating layer (240), the forming of a trench (244) in a portion of the isolating layer (240) positioned on the face (220).

Abstract: A method for determining, in a first semiconductor material wafer having at least one through via, mechanical stress induced by the at least one through via, this method including the steps of: manufacturing a test structure from a second wafer of the same nature as the first wafer, in which the at least one through via is formed by a substantially identical method, a rear surface layer being further arranged on this second wafer so that the via emerges on the layer; measuring the mechanical stress in the rear surface layer; and deducing therefrom the mechanical stress induced in the first semiconductor material wafer.