Abstract: In an adder that finds the sum of two binary numbers A and B, it is now conventional to associate one or more parity bits (PA, PB, PS) with each of the two numbers A and B and the result S. Each number A and B and the result S is divided into K groups each of m bits, and one parity bit is associated with each group. In accordance with the invention, the parity PS associated with the result S is obtained at the same time as the result. The input carry bit c.sub.i n intervening in the addition is available before the beginning of operations. Consequently, it is used in a first stage 10' upstream of the device, which calculates intermediate variables p.sub.i,j and g.sub.i,j. The other input carry bits c.sub.i,1 corresponding to the other groups are determined only later by a carry look ahead circuit, and consequently they are used only in a second stage 50' downstream of the device. The use of c.sub.