Patents by Inventor Pascal FONTENEAU

Pascal FONTENEAU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210288102
    Abstract: Image sensors and methods of manufacturing image sensors are provided herein. In an embodiment, a method of manufacturing an image sensor includes forming a structure having a front side and a back side. The structure includes a semiconductor layer extending between the front side and the back side of the structure, and a capacitive insulation wall extending through the semiconductor layer between the front side and the back side of the structure. The capacitive insulation wall includes first and second insulating walls separated by a region of a conductive or semiconductor material. The method further includes selectively etching, from the back side of the structure, portions of the semiconductor layer and the region of conductive or semiconductor material, while retaining adjacent portions of the first and second insulating walls.
    Type: Application
    Filed: May 21, 2021
    Publication date: September 16, 2021
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Frederic LALANNE, Laurent GAY, Pascal FONTENEAU, Yann HENRION, Francois GUYADER
  • Publication number: 20210193849
    Abstract: The present disclosure concerns a photodiode including at least one memory area, each memory area including at least two charge storage regions.
    Type: Application
    Filed: December 17, 2020
    Publication date: June 24, 2021
    Inventors: Arnaud TOURNIER, Boris RODRIGUES GONCALVES, Frederic LALANNE, Pascal FONTENEAU
  • Patent number: 11031433
    Abstract: Image sensors and methods of manufacturing image sensors are provided herein. In an embodiment, a method of manufacturing an image sensor includes forming a structure having a front side and a back side. The structure includes a semiconductor layer extending between the front side and the back side of the structure, and a capacitive insulation wall extending through the semiconductor layer between the front side and the back side of the structure. The capacitive insulation wall includes first and second insulating walls separated by a region of a conductive or semiconductor material. The method further includes selectively etching, from the back side of the structure, portions of the semiconductor layer and the region of conductive or semiconductor material, while retaining adjacent portions of the first and second insulating walls.
    Type: Grant
    Filed: February 8, 2019
    Date of Patent: June 8, 2021
    Assignee: STMicroelectronics (Crolles) SAS
    Inventors: Frederic Lalanne, Laurent Gay, Pascal Fonteneau, Yann Henrion, Francois Guyader
  • Patent number: 10978487
    Abstract: An inverter includes a semiconductor substrate. A Z2-FET switch is disposed at a first surface of the semiconductor substrate and a further switch is disposed at the first surface of the semiconductor substrate. The further switch and the Z2-FET switch have current paths coupled between a first reference terminal and a second reference terminal.
    Type: Grant
    Filed: February 28, 2019
    Date of Patent: April 13, 2021
    Assignees: STMICROELECTRONICS (CROLLES 2) SAS, STMICROELECTRONICS SA
    Inventors: Hassan El Dirani, Pascal Fonteneau
  • Publication number: 20200227451
    Abstract: Image sensors and methods of manufacturing image sensors are provided. One such method includes forming a structure that includes a semiconductor layer extending from a front side to a back side, and a capacitive insulation wall extending through the semiconductor layer. The capacitive insulation wall includes first and second insulating walls separated by a region of a conductor or a semiconductor material. Portions of the semiconductor layer and the region of the conductor or semiconductor material are selectively etched, and the first and second insulating walls have portions protruding outwardly beyond a back side of the semiconductor layer and of the region of the conductor or semiconductor material. A dielectric passivation layer is deposited on the back side of the structure, and portions of the dielectric passivation layer are locally removed on a back side of the protruding portions of the first and second insulating walls.
    Type: Application
    Filed: January 10, 2020
    Publication date: July 16, 2020
    Inventors: Laurent GAY, Frederic LALANNE, Yann HENRION, Francois GUYADER, Pascal FONTENEAU, Aurelien SEIGNARD
  • Publication number: 20190341478
    Abstract: A Z2-FET-type structure includes a first front gate, a second front gate, a first back gate doped with p-type dopants, and a second back gate doped with n-type dopants. The structure may also include a buried insulating layer between the front gates and the back gates, an anode region, a cathode region, and an intermediate region separating the anode region and the cathode region.
    Type: Application
    Filed: April 30, 2019
    Publication date: November 7, 2019
    Inventors: Hassan El Dirani, Pascal Fonteneau
  • Publication number: 20190288005
    Abstract: An inverter includes a semiconductor substrate. A Z2-FET switch is disposed at a first surface of the semiconductor substrate and a further switch is disposed at the first surface of the semiconductor substrate. The further switch and the Z2-FET switch have current paths coupled between a first reference terminal and a second reference terminal.
    Type: Application
    Filed: February 28, 2019
    Publication date: September 19, 2019
    Inventors: Hassan El Dirani, Pascal Fonteneau
  • Publication number: 20190252457
    Abstract: Image sensors and methods of manufacturing image sensors are provided herein. In an embodiment, a method of manufacturing an image sensor includes forming a structure having a front side and a back side. The structure includes a semiconductor layer extending between the front side and the back side of the structure, and a capacitive insulation wall extending through the semiconductor layer between the front side and the back side of the structure. The capacitive insulation wall includes first and second insulating walls separated by a region of a conductive or semiconductor material. The method further includes selectively etching, from the back side of the structure, portions of the semiconductor layer and the region of conductive or semiconductor material, while retaining adjacent portions of the first and second insulating walls.
    Type: Application
    Filed: February 8, 2019
    Publication date: August 15, 2019
    Inventors: Frederic LALANNE, Laurent GAY, Pascal FONTENEAU, Yann HENRION, Francois GUYADER
  • Patent number: 10312240
    Abstract: A microelectronic component is capable of being used as a memory cell. The component includes a semiconductor layer resting on an insulating layer and including a doped source region of a first conductivity type, a doped drain region of a second conductivity type, and an intermediate region, non-doped or more lightly doped, with the second conductivity type, than the drain region, the intermediate region including first and second portions respectively extending from the drain region and from the source region. An insulated front gate electrode rests on the first portion. A first back gate electrode and a second back gate electrode are arranged under the insulating layer, respectively opposite the first portion and the second portion.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: June 4, 2019
    Assignee: STMICROELECTRONICS SA
    Inventors: Hassan El Dirani, Yohann Solaro, Pascal Fonteneau
  • Patent number: 10062681
    Abstract: A protection device for protecting an IC against electrostatic discharge includes a buried insulant layer having a thickness that is no greater than fifty nanometers with bipolar transistors arranged thereon, one of which is NPN and the other of which is PNP. A base of one merges with a collector of the other. The transistors selectively conduct a discharge current between electrodes. A first semiconductor ground plane under the buried insulant layer is capable of being electrically biased and extends underneath the base of the first bipolar transistor. The ground plane and a base of one transistor have the same doping. However, its dopant density is at least tenfold greater than that of the base.
    Type: Grant
    Filed: May 10, 2017
    Date of Patent: August 28, 2018
    Assignees: Commissariat à l'énergie atomique et aux énergies alternatives, STMicroelectronics SA, Centre National de la Recherche Scientifique
    Inventors: Yohann Solaro, Sorin Cristoloveanu, Claire Fenouillet-Beranger, Pascal Fonteneau
  • Publication number: 20180138181
    Abstract: A microelectronic component is capable of being used as a memory cell. The component includes a semiconductor layer resting on an insulating layer and including a doped source region of a first conductivity type, a doped drain region of a second conductivity type, and an intermediate region, non-doped or more lightly doped, with the second conductivity type, than the drain region, the intermediate region including first and second portions respectively extending from the drain region and from the source region. An insulated front gate electrode rests on the first portion. A first back gate electrode and a second back gate electrode are arranged under the insulating layer, respectively opposite the first portion and the second portion.
    Type: Application
    Filed: January 11, 2018
    Publication date: May 17, 2018
    Inventors: Hassan El Dirani, Yohann Solaro, Pascal Fonteneau
  • Publication number: 20180061838
    Abstract: A microelectronic component is capable of being used as a memory cell. The component includes a semiconductor layer resting on an insulating layer and including a doped source region of a first conductivity type, a doped drain region of a second conductivity type, and an intermediate region, non-doped or more lightly doped, with the second conductivity type, than the drain region, the intermediate region including first and second portions respectively extending from the drain region and from the source region. An insulated front gate electrode rests on the first portion. A first back gate electrode and a second back gate electrode are arranged under the insulating layer, respectively opposite the first portion and the second portion.
    Type: Application
    Filed: March 21, 2017
    Publication date: March 1, 2018
    Inventors: Hassan El Dirani, Yohann Solaro, Pascal Fonteneau
  • Patent number: 9905565
    Abstract: A microelectronic component is capable of being used as a memory cell. The component includes a semiconductor layer resting on an insulating layer and including a doped source region of a first conductivity type, a doped drain region of a second conductivity type, and an intermediate region, non-doped or more lightly doped, with the second conductivity type, than the drain region, the intermediate region including first and second portions respectively extending from the drain region and from the source region. An insulated front gate electrode rests on the first portion. A first back gate electrode and a second back gate electrode are arranged under the insulating layer, respectively opposite the first portion and the second portion.
    Type: Grant
    Filed: March 21, 2017
    Date of Patent: February 27, 2018
    Assignee: STMicroelectronics SA
    Inventors: Hassan El Dirani, Yohann Solaro, Pascal Fonteneau
  • Publication number: 20170256531
    Abstract: A protection device for protecting an IC against electrostatic discharge includes a buried insulant layer having a thickness that is no greater than fifty nanometers with bipolar transistors arranged thereon, one of which is NPN and the other of which is PNP. A base of one merges with a collector of the other. The transistors selectively conduct a discharge current between electrodes. A first semiconductor ground plane under the buried insulant layer is capable of being electrically biased and extends underneath the base of the first bipolar transistor. The ground plane and a base of one transistor have the same doping. However, its dopant density is at least tenfold greater than that of the base.
    Type: Application
    Filed: May 10, 2017
    Publication date: September 7, 2017
    Inventors: Yohann Solaro, Sorin Cristoloveanu, Claire Fenouillet-Beranger, Pascal Fonteneau
  • Patent number: 9666577
    Abstract: The invention relates to an IC with an electrostatic discharge protection device. There is a buried insulant layer 50 nm or less in thickness and first and second bipolar transistors on the insulant layer, one being an npn transistor and the other a pnp transistor. The base of the first transistor is merged with the collector of the second transistor and the base of the second transistor is merged with the collector of the first transistor. The first and second bipolar transistors are configured to selectively conduct a discharge current between two electrodes of the protection device. There is a first semiconductor ground plane under the insulant layer, being electrically biased, extending until it is plumb with the base of the first bipolar transistor, exhibiting a first type of doping identical to that of the base of the first bipolar transistor with a doping density at least ten times greater.
    Type: Grant
    Filed: August 4, 2014
    Date of Patent: May 30, 2017
    Assignees: Commissariat à l'énergie atomique et aux énergies alternatives, STMicroelectronics SA, Centre National De La Recherche Scientifique
    Inventors: Yohann Solaro, Sorin Cristoloveanu, Claire Fenouillet-Beranger, Pascal Fonteneau
  • Patent number: 9653476
    Abstract: An integrated circuit includes a transistor, an UTBOX buried insulating layer disposed under it and a ground plane disposed under the layer. A well is disposed under the plane and a first trench is at the periphery of the transistor and extends through the layer into the well. There is a substrate under the well and a p-n diode on a side of the transistor. The diode comprises first and second zones of opposite doping and the first zone is configured for electrical connection to a first electrode of the transistor. The first and second zones are coplanar with the plane and a second trench for separating the first and second zones. The second trench extends through the layer into the plane to a depth less than an interface between the plane and the well. There is a third zone under the second trench forming a junction between the zones.
    Type: Grant
    Filed: July 2, 2013
    Date of Patent: May 16, 2017
    Assignees: Commissariate a l'energie atomique et aux energies alternatives, STMicroelectronics SA
    Inventors: Claire Fenouillet-Beranger, Pascal Fonteneau
  • Patent number: 9530922
    Abstract: An overvoltage protection component may be in a SOI layer, a portion of the SOI layer forming the core of an optical waveguide. This component may be made of semiconductor regions of different doping types and/or levels, at least one of these regions corresponding to at least a portion of the waveguide core.
    Type: Grant
    Filed: September 25, 2014
    Date of Patent: December 27, 2016
    Assignee: STMICROELECTRONICS SA
    Inventor: Pascal Fonteneau
  • Patent number: 9478570
    Abstract: The present disclosure relates to a photodiode comprising: a P-conductivity type substrate region, an electric charge collecting region for collecting electric charges appearing when a rear face of the substrate region receives light, the collecting region comprising an N-conductivity type region formed deep in the substrate region, an N-conductivity type read region formed in the substrate region, and an isolated transfer gate, formed in the substrate region in a deep isolating trench extending opposite a lateral face of the N-conductivity type region, next to the read region, and arranged for receiving a gate voltage to transfer electric charges stored in the collecting region toward the read region.
    Type: Grant
    Filed: October 30, 2015
    Date of Patent: October 25, 2016
    Assignees: STMICROELECTRONICS SA, STMICROELECTRONICS (CROLLES 2) SAS
    Inventors: Jean-Robert Manouvrier, Pascal Fonteneau, Xavier Montagner
  • Patent number: 9453977
    Abstract: A device includes integrated circuit chips mounted on one another. At least one component for protecting elements of a first one of the chips is formed in a second one of the chips. Preferably, the chips are of SOI type, the second chip includes an SOI layer having a first thickness sufficient to support the component for protecting elements. The first chip also includes an SOI layer but having a second thickness smaller than the first thickness that is insufficient to support the component for protecting elements. The SOI layer of the second chip may be an optical waveguide layer.
    Type: Grant
    Filed: April 28, 2016
    Date of Patent: September 27, 2016
    Assignee: STMicroelectronics SA
    Inventor: Pascal Fonteneau
  • Publication number: 20160238806
    Abstract: A device includes integrated circuit chips mounted on one another. At least one component for protecting elements of a first one of the chips is formed in a second one of the chips. Preferably, the chips are of SOI type, the second chip includes an SOI layer having a first thickness sufficient to support the component for protecting elements. The first chip also includes an SOI layer but having a second thickness smaller than the first thickness that is insufficient to support the component for protecting elements. The SOI layer of the second chip may be an optical waveguide layer.
    Type: Application
    Filed: April 28, 2016
    Publication date: August 18, 2016
    Applicant: STMicroelectronics SA
    Inventor: Pascal Fonteneau