Abstract: The method for automated manufacturing of an electronic circuit tolerant to faults by temporal redundancy of maximum order N, comprising a step implemented by computer, according to which every memory cell of the circuit is replaced by a memory block (40) comprising a chain of memory cells in series, and a selection block which, in a temporal redundancy mode of order n1, n1?[1,N], selects as output data of the memory block the majority content of n1 cells of the block, and can furthermore deliver a fault signal if the contents of the n1 cells differ. Said method is characterized in that the inserted memory blocks allow a dynamic switching from a temporal redundancy mode of order n1 to any other mode of order n2. Said method for N=2, in association with a mechanism for recording with roll-back, allows an error with only a double redundancy instead of a triple redundancy.

Abstract: The invention relates to a method for verifying transformation (2) of a source code (1) into a transformed code (3) designed for an embedded system (7) such as in a smart card or other portable or mobile device including data processing resources. The method comprises at least the following steps: determining a single virtual machine that factors in the behavior of both of these codes (1, 3), determining for each source code (1) and transformed code (3) a plurality of auxiliary functions representing the residual differences between said source code (1) and transformed code (3), and a step for verifying a correspondence property between the auxiliary functions, the verification of the code transformation (2) being obtained from this last step.