Patents by Inventor Pascal Guenard
Pascal Guenard has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20180309426Abstract: A production method for a surface acoustic wave device comprises the following steps: a step of providing a piezoelectric substrate comprising a transducer arranged on the main front face; a step of depositing a dielectric encapsulation layer on the main front face of the piezoelectric substrate and on the transducer; and a step of assembling the dielectric encapsulation layer with the main front face of a support substrate having a coefficient of thermal expansion less than that of the piezoelectric substrate. In additional embodiments, a surface acoustic wave device comprises a layer of piezoelectric material equipped with a transducer on a main front face, arranged on a substrate support of which the coefficient of thermal expansion is less than that of the piezoelectric material. The transducer is arranged in a dielectric encapsulation layer, between the layer of piezoelectric material and the support substrate.Type: ApplicationFiled: October 17, 2016Publication date: October 25, 2018Inventors: Pascal Guenard, Ionut Radu
-
Patent number: 9865786Abstract: The disclosure relates to a manufacturing method comprising the formation of elemental LED or photovoltaic structures on a first substrate, each comprising at least one p-type layer, an active zone and an n-type layer, formation of a first planar metal layer on the elemental structures, provision of a transfer substrate comprising a second planar metal layer, assembly of the elemental structures with the transfer substrate by bonding of the first and second metal layers by molecular adhesion at room temperature, and removal of the first substrate.Type: GrantFiled: October 24, 2016Date of Patent: January 9, 2018Assignee: SoitecInventor: Pascal Guenard
-
Publication number: 20170040518Abstract: The disclosure relates to a manufacturing method comprising the formation of elemental LED or photovoltaic structures on a first substrate, each comprising at least one p-type layer, an active zone and an n-type layer, formation of a first planar metal layer on the elemental structures, provision of a transfer substrate comprising a second planar metal layer, assembly of the elemental structures with the transfer substrate by bonding of the first and second metal layers by molecular adhesion at room temperature, and removal of the first substrate.Type: ApplicationFiled: October 24, 2016Publication date: February 9, 2017Inventor: Pascal Guenard
-
Patent number: 9478707Abstract: The disclosure relates to a manufacturing method comprising the formation of elemental LED or photovoltaic structures on a first substrate, each comprising at least one p-type layer, an active zone and an n-type layer, formation of a first planar metal layer on the elemental structures, provision of a transfer substrate comprising a second planar metal layer, assembly of the elemental structures with the transfer substrate by bonding of the first and second metal layers by molecular adhesion at room temperature, and removal of the first substrate.Type: GrantFiled: June 14, 2013Date of Patent: October 25, 2016Assignee: SoitecInventor: Pascal Guenard
-
Patent number: 9412904Abstract: A device for back-scattering an incident light ray, including: a host substrate; a structured layer; a first face in contact with a front face of the host substrate; a second flat face parallel to the first face; a first material and a second material which form, in a mixed plane, alternating surfaces at least one of whose dimensions is between 300 nm and 800 nm, the mixed plane is between the first and second face of the structured layer; wherein the refractive index of the first and of the second material are different, the structured layer is covered by a specific layer, the specific layer is made of a material which is different from the first and second materials of the structured layer, and the specific layer is crystalline and semi-conductive.Type: GrantFiled: January 4, 2013Date of Patent: August 9, 2016Assignees: Commissariat a l'energie atomique et aux energies alternatives, SoitecInventors: Yohan Desieres, Philippe Gilet, Pascal Guenard
-
Patent number: 9224921Abstract: The invention relates to a method for fabricating a structure including a semiconductor material comprising: a) implanting one or more ion species to form a weakened region delimiting at least one seed layer in a substrate of semiconductor material, b) forming, before or after step a), at least one metallic layer on the substrate in semiconductor material, c) assembling the at least one metallic layer with a transfer substrate, then fracturing the implanted substrate at the weakened region, and d) forming at least one layer in semiconductor material on the at least one seed layer, for example, by epitaxy.Type: GrantFiled: November 16, 2011Date of Patent: December 29, 2015Assignee: SOITECInventors: Jean-Marc Bethoux, Pascal Guenard
-
Publication number: 20150155331Abstract: The disclosure relates to a method of collective manufacturing of light-emitting diode (LED) devices comprising formation of elemental structures, each comprising an n-type layer, an active layer and a p-type layer, the method comprising: —reduction of the lateral dimensions of part of each elemental LED structure; —formation of a portion of insulating material on the sides of the elemental structures; —formation of n-type electrical contact pads and p-type electrical contact pads; —deposition of a conductive material layer; on the elemental structures and polishing of the conductive material layer; and—bonding by molecular adhesion of a second substrate on the polished surface of the structure.Type: ApplicationFiled: June 18, 2013Publication date: June 4, 2015Inventor: Pascal Guenard
-
Patent number: 9041165Abstract: A method for the formation of an at least partially relaxed strained material layer, comprises providing a seed substrate; patterning the seed substrate; growing a strained material layer on the patterned seed substrate; transferring the strained material layer from the patterned seed substrate to an intermediate substrate; and at least partially relaxing the strained material layer by a heat treatment.Type: GrantFiled: January 11, 2010Date of Patent: May 26, 2015Assignee: SOITECInventors: Fabrice Letertre, Bruce Faure, Pascal Guenard
-
Publication number: 20150115290Abstract: The invention disclosure relates to a manufacturing method comprising the formation of elemental LED or photovoltaic structures on a first substrate, each comprising at least one p-type layer, an active zone and an n-type layer, formation of a first planar metal layer on the elemental structures, provision of a transfer substrate comprising a second planar metal layer, assembly of the elemental structures with the transfer substrate by bonding of the first and second metal layers by molecular adhesion at room temperature, and removal of the first substrate.Type: ApplicationFiled: June 14, 2013Publication date: April 30, 2015Inventor: Pascal Guenard
-
Publication number: 20150001568Abstract: A device for back-scattering an incident light ray, including: a host substrate; a structured layer; a first face in contact with a front face of the host substrate; a second flat face parallel to the first face; a first material and a second material which form, in a mixed plane, alternating surfaces at least one of whose dimensions is between 300 nm and 800 nm, the mixed plane is between the first and second face of the structured layer; wherein the refractive index of the first and of the second material are different, the structured layer is covered by a specific layer, the specific layer is made of a material which is different from the first and second materials of the structured layer, and the specific layer is crystalline and semi-conductive.Type: ApplicationFiled: January 4, 2013Publication date: January 1, 2015Applicants: Commissariaat a I'energie atomique et aux ene alt, SOITECInventors: Yohan Desieres, Philippe Gilet, Pascal Guenard
-
Patent number: 8785293Abstract: The invention relates to a method of adapting the lattice parameter of a seed layer of a strained material, comprising the following successive steps: a) a structure is provided that has a seed layer of strained material, of lattice parameter A1, of nominal lattice parameter An and of thermal expansion coefficient CTE3, a low-viscosity layer and an intermediate substrate of thermal expansion coefficient CTE1; b) a heat treatment is applied so as to relax the seed layer of strained material; and c) the seed layer is transferred onto a support substrate of thermal expansion coefficient CTE5, the intermediate substrate and the support substrate being chosen so that A1<An and CTE1?CTE3 and CTE5>CTE1 or A1>An and CTE1?CTE3 and CTE5<CTE1.Type: GrantFiled: February 15, 2010Date of Patent: July 22, 2014Assignee: SOITECInventors: Pascal Guenard, Frederic Dupont
-
Publication number: 20130285067Abstract: The invention relates to a method for fabricating a structure including a semiconductor material comprising: a) implanting one or more ion species to form a weakened region delimiting at least one seed layer in a substrate of semiconductor material, b) forming, before or after step a), at least one metallic layer on the substrate in semiconductor material, c) assembling the at least one metallic layer with a transfer substrate, then fracturing the implanted substrate at the weakened region, d) forming at least one layer in semiconductor material on the at least one seed layer, for example, by epitaxy.Type: ApplicationFiled: November 16, 2011Publication date: October 31, 2013Inventors: Jean-Marc Bethoux, Pascal Guenard
-
Patent number: 8492244Abstract: The present invention provides methods for forming at least partially relaxed strained material layers on a target substrate. The methods include forming islands of the strained material layer on an intermediate substrate, at least partially relaxing the strained material islands by a first heat treatment, and transferring the at least partially relaxed strained material islands to the target substrate. The at least partial relaxation is facilitated by the presence of low-viscosity or compliant layers adjacent to the strained material layer. The invention also provides semiconductor structures having an at least partially relaxed strained material layer, and semiconductor devices fabricated using an at least partially relaxed strained material layer.Type: GrantFiled: April 7, 2011Date of Patent: July 23, 2013Assignee: SoitecInventors: Pascal Guenard, Bruce Faure, Fabrice Letertre, Michael R. Krames, Nathan F. Gardner, Melvin B. McLaurin
-
Publication number: 20120199956Abstract: The present invention relates to process for recycling a source substrate that has a surface region and regions in relief on the surface region, with the regions in relief corresponding to residual regions of a layer of the source substrate that were not being separated from the rest of the source substrate during a prior removal step. The process includes selective electromagnetic irradiation of the source substrate at a wavelength such that the damaged material of the surface region absorbs the electromagnetic irradiation. The present invention also relates to a recycled source substrate and to a process for transferring a layer from a source substrate recycled for this purpose.Type: ApplicationFiled: February 7, 2012Publication date: August 9, 2012Inventors: Monique Lecomte, Pascal Guenard, Sophie Rigal, David Sotta, Fabienne Janin, Christelle Veytizou
-
Publication number: 20110294245Abstract: The invention relates to a method of adapting the lattice parameter of a seed layer of a strained material, comprising the following successive steps: a) a structure is provided that has a seed layer of strained material, of lattice parameter A1, of nominal lattice parameter An and of thermal expansion coefficient CTE3, a low-viscosity layer and an intermediate substrate of thermal expansion coefficient CTE1; b) a heat treatment is applied so as to relax the seed layer of strained material; and c) the seed layer is transferred onto a support substrate of thermal expansion coefficient CTE5, the intermediate substrate and the support substrate being chosen so that A1<An and CTE1?CTE3 and CTE5>CTE1 or A1>An and CTE1?CTE3 and CTE5<CTE1.Type: ApplicationFiled: February 15, 2010Publication date: December 1, 2011Applicant: S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIESInventors: Pascal Guenard, Frederic Dupont
-
Publication number: 20110291247Abstract: The present invention relates to a method for the formation of an at least partially relaxed strained material layer, the method comprising the steps of providing a seed substrate; patterning the seed substrate; growing a strained material layer on the patterned seed substrate; transferring the strained material layer from the patterned seed substrate to an intermediate substrate; and at least partially relaxing the strained material layer by a heat treatment.Type: ApplicationFiled: January 11, 2010Publication date: December 1, 2011Applicant: S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIESInventors: Fabrice Letertre, Bruce Faure, Pascal Guenard
-
Publication number: 20110180911Abstract: The present invention provides methods for forming at least partially relaxed strained material layers on a target substrate. The methods include forming islands of the strained material layer on an intermediate substrate, at least partially relaxing the strained material islands by a first heat treatment, and transferring the at least partially relaxed strained material islands to the target substrate. The at least partial relaxation is facilitated by the presence of low-viscosity or compliant layers adjacent to the strained material layer. The invention also provides semiconductor structures having an at least partially relaxed strained material layer, and semiconductor devices fabricated using an at least partially relaxed strained material layer.Type: ApplicationFiled: April 7, 2011Publication date: July 28, 2011Inventors: Pascal Guenard, Bruce Faure, Fabrice Letertre, Michael R. Krames, Nathan F. Gardner, Melvin B. McLaurin
-
Patent number: 7981767Abstract: The present invention provides methods for forming at least partially relaxed strained material layers on a target substrate. The methods include forming islands of the strained material layer on an intermediate substrate, at least partially relaxing the strained material islands by a first heat treatment, and transferring the at least partially relaxed strained material islands to the target substrate. The at least partial relaxation is facilitated by the presence of low-viscosity or compliant layers adjacent to the strained material layer. The invention also provides semiconductor structures having an at least partially relaxed strained material layer, and semiconductor devices fabricated using an at least partially relaxed strained material layer.Type: GrantFiled: December 22, 2008Date of Patent: July 19, 2011Assignee: S.O.I.Tec Silicon on Insulator TechnologiesInventors: Pascal Guenard, Bruce Faure, Fabrice Letertre, Michael R. Krames, Nathan F. Gardner, Melvin B. McLaurin
-
Patent number: 7736935Abstract: The present invention provides, in part, methods producing multilayer semiconductor structures having one or more at least partially relaxed strained layers, where the strained layer is at least partially relaxed by annealing. In particular, the invention forms diffusion barriers that prevent diffusion of contaminants during annealing. The invention also includes embodiments where the at least partially relaxed strained layer is patterned into islands by etching trenches and the like. The invention also provides semiconductor structures resulting from these methods, and further, provides such structures where the semiconductor materials are suitable for application to LED devices, laser devices, photovoltaic devices, and other optoelectronic devices.Type: GrantFiled: December 22, 2008Date of Patent: June 15, 2010Assignee: S.O.I.Tec Silicon on Insulator TechnologiesInventors: Bruce Faure, Pascal Guenard
-
Publication number: 20100032793Abstract: The present invention provides methods for forming at least partially relaxed strained material layers on a target substrate. The methods include forming islands of the strained material layer on an intermediate substrate, at least partially relaxing the strained material islands by a first heat treatment, and transferring the at least partially relaxed strained material islands to the target substrate. The at least partial relaxation is facilitated by the presence of low-viscosity or compliant layers adjacent to the strained material layer. The invention also provides semiconductor structures having an at least partially relaxed strained material layer, and semiconductor devices fabricated using an at least partially relaxed strained material layer.Type: ApplicationFiled: December 22, 2008Publication date: February 11, 2010Inventors: Pascal Guenard, Bruce Faure, Fabrice Letertre, Michael R. Krames, Nathan F. Gardner, Melvin B. McLaurin