Abstract: A processing system includes a processor (20) having an idle mode node for generating an idle mode signal indicating whether the processor is in an idle mode and a memory (22) having a data retention node for receiving a data retention mode signal. The memory includes circuitry for placing the memory in a low power state responsive to the data retention mode signal. The idle mode signal drives the data retention node, such that the memory is placed in the low power state when the processor is in idle mode.

Abstract: A processing system includes a processor (20) having an idle mode node for generating an idle mode signal indicating whether the processor is in an idle mode and a memory (22) having a data retention node for receiving a data retention mode signal. The memory includes circuitry for placing the memory in a low power state responsive to the data retention mode signal. The idle mode signal drives the data retention node, such that the memory is placed in the low power state when the processor is in idle mode.

Abstract: A voltage controlled oscillator (38) includes an LC tank (20) and a capacitor bank (21). LC tank (20) includes an inductor (12) and a varactor (14). The capacitive output of the varactor is controlled by a control voltage &ngr;. To electronically tune the voltage controlled oscillator, a set of capacitors (24) in the capacitor bank (21) are enabled by a digital control signal based on a frequency comparison with a desired frequency. Once the capacitor bank is set, the frequency can be locked at the desired frequency by the phase lock loop.

Abstract: An oscillator includes a resonator, such as a crystal (12) coupled to first and second capacitor banks (14). The first and second capacitor banks (14) each comprise a plurality of capacitors (16) coupled to the resonator (12) through respective switching devices (18) that may be selectively enabled. The switches (18) are selectively enabled to couple a desired set of said capacitors (16) to said resonator (12). At least one of the switches (18sd) is controlled with a clock signal having a programmable duty cycle from a sigma-delta modulator (20) to enable at least one of said capacitors (16sd) during a first phase of the clock signal and disable that capacitor (16sd) during a second phase of the clock signal.

Abstract: A voltage controlled oscillator (38) includes an LC tank (20) and a capacitor bank (21). LC tank (20) includes an inductor (12) and a varactor (14). The capacitive output of the varactor is controlled by a control voltage &ngr;. To electronically tune the voltage controlled oscillator, a set of capacitors (24) in the capacitor bank (21) are enabled by a digital control signal based on a frequency comparison with a desired frequency. Once the capacitor bank is set, the frequency can be locked at the desired frequency by the phase lock loop.

Abstract: Current bit cell having a current source (P1), a transistor (P6) for detecting the presence of a digital signal bit (Bit) and a plurality of transistors (P2, P5, P7) for detecting at least one command signal (L, Lc) so as to command, on a first output (S1) of the cell, the appearance of a current delivered by the current source (P1) as a function of the digital signal (Bit) applied to the cell and of the at least one command signal (L, Lc), a transistor (P9) for detecting the presence of a bit (Bitz) complementary to the bit of the digital signal (Bit) and a plurality of transistors (P3, P4, P8) for detecting the complement (Lz, Lcz) of the at least one command signal (L, Lc), so as to command on a second output (S2) of the cell the appearance of a current delivered by the current source (P1) which is the complement of the current delivered on the first output (S1), the transistors for detecting the presence of bits and of the at least one command signal, the transistors for detecting the presence of compleme

Abstract: Delay circuit comprising a delay cell formed by a current source (I) connected between drain and source of two field-effect transistors (PO, NO) whose gates are connected to each other in order to constitute the input of the cell, and an inverter (INV) linked to one or other of the terminals of the current source (I) according to whether the delay is to affect the leading edge or the trailing edge of the signal to be delayed, a capacitor (C) for defining a delay time (Te) proportional to the power supply voltage and inversely proportional to the current (I) delivered by the current source, being connected between the input of the inverter (INV) and earth, characterized in that it furthermore comprises a circuit (Ci, Cu, S1, S3, AMPLO, P1) for regulating the current delivered by the current source in order to make it proportional to the power supply voltage of the circuit.

Abstract: Controlled delay digital clock signal generator, characterised in that it comprises means (I5, I6, I7, I8, I9, I10, IT7, IT8, IT9, IT10, C4) to generate from a clock signal (CK) and its complementary signal (CKB) a ramp signal comprising at least two segments of positive slope and at least two segments of negative slope, means (I1, I2, IT1, IT2, IT3, C2, CET1T2, AMPLI, I3, I4, IT4, IT5, IT6, C3, CET3T4, AMPL2) for separate control of the slopes of the said segments, means with trigger circuits (AMPLO) for converting the ramp signal (RAMP) into a square signal (CKQ) means (NO0, A0, A1, NO1) for achieving the logic combinations of the delayed square clock signal (CKQ) resulting from the conversion with the clock signal (CK) and the clock complementary clock signal (CKB) of the said clock signal to obtain as many delayed digital clock signals as the ramp signal has segments of different slopes.