Abstract: A microprocessor includes a counter having a counting input and a reset input. The counting input is coupled to a first terminal of the microprocessor for the selection of an operating mode thereof by application of a predetermined number of pulses to the first terminal. The reset input of the counter is driven by a control signal present on a second terminal of the microprocessor. The control signal is maintained by default at a first logic value ensuring the maintaining at zero of the counter during the initialization period by a circuit internal or external the microprocessor. Immunity against electromagnetic perturbations causing the microprocessor to enter into the test mode is provided.

Abstract: A device for read protection of at least one area of a non-volatile memory includes an address decoder outputting an addressing signal on one of its output terminals when an the address corresponds to one of the read protected areas of the memory. A state memory is provided for each read protected area to output a state signal indicating whether or not the area is protected in read. A program instructions decoder outputs a program signal indicating whether or not the current addressing operation corresponds to a program instruction. A logic circuit responsive to the addressing signal, the state signal and the program signal outputs an instruction signal to read the read protected area when the program signal indicates that the current addressing operation is applicable to a program instruction.

Abstract: The invention concerns a device for read-protection of at least a zone of a non-volatile storage (10), characterised in that it comprises: an address decoder (40) for supplying on one of the output terminals an addressing signal (NSWHADOW1SEL, NSWHADOWnSEL) when the address corresponds to one of the read-protected zones of the storage (10); a state storage (Mn1,Mn) for each read-protected zone for supplying a state signal (PMPR1, PMPRn) indicating whether the zone is read-protected or not; a programme instruction decoder (DIP) for supplying a programme signal (OP) indicating whether the current addressing operation corresponds or not to a programme instruction; and a logic circuit (42), whereto are applied the addressing signal (NSWHADOW1SEL, NSWHADOWnSEL), the state signal (PMPR1, PMPRn) and the programme signal (OP), for supplying an instruction signal (R10) for reading the read-protected zone when the programme signal (OP) indicates that the current addressing operation concerns a programme instruction.

Abstract: A microprocessor includes a counter having a counting input and a reset input. The counting input is coupled to a first terminal of the microprocessor for the selection of an operating mode thereof by application of a predetermined number of pulses to the first terminal. The reset input of the counter is driven by a control signal present on a second terminal of the microprocessor. The control signal is maintained by default at a first logic value ensuring the maintaining at zero of the counter during the initialization period by a circuit internal or external the microprocessor. Immunity against electromagnetic perturbations causing the microprocessor to enter into the test mode is provided.