Abstract: A method and an apparatus for handling interrupt requests generated by a plurality of interrupt sources (2A, 2N) for a processor. The method includes steps of scanning interrupt registering means (8) for determining a current interrupt request to be sent to the processor among interrupt requests having respective interrupt flags inputted in said interrupt registering means, and steps involving the processor for execution of an interrupt processing program according to the result of a comparison of a scanned interrupt flag with a predetermined flag value, characterised in that it includes a step of latching a flag corresponding to a first occurring interrupt request from a source in a group of sources into interrupt latch registering means (7) for further processing and for blocking further interrupt requests from at least the same source in the same group from having a flag latched before processor controlled resetting.

Abstract: The desynchronizer stores information units corresponding to time slots of a PCM-stream (IN) in consecutive memory locations of a buffer memory (BM). The number of memory locations of this memory (BM) corresponds to the length of a subframe within which the desynchronizer substantially randomizes the order of the information units. This randomization is achieved by reading the stored information units in an order dictated by a permutation (A1) of the addresses of the memory locations. This permutation (A1) is substantially randomly selected from the limited number of possible permutations by a permutation device (PM) and is started simultaneously with the arrival of the first information unit of a subframe. In order to ensure that all information units are forwarded to the output stream (OUT) the mentioned permutation is repeated (A2) by a permutation repetition device (PRM) simultaneously with a new permutation (A1) corresponding to a next subframe.