Abstract: The present description concerns a memory module (100) adapted to implementing computing operations, the module comprising a plurality of elementary blocks (110) arranged in an array according to rows and columns, wherein: each elementary block (110) comprises a memory circuit (111) adapted to implementing computing operations, and a configurable transfer circuit (113); each configurable transfer circuit (113) is parameterizable to transmit data originating from a first transmit elementary block to a receive elementary block of a same column of elementary blocks via at least one link bus; an internal control circuit (120) is connected to an input-output port (123) of the module; and the internal control circuit (120) is configured to read at least one instruction signal from the input-output port (123) of the module and accordingly parameterize the configuration of the configurable transfer circuits (113), and define the size of the operand vectors of the computing operations.

Abstract: The present description concerns a memory device (200) comprising: a memory circuit (201) implementing operations and performing elementary operations including a reading, a writing, or a computing operation; a control circuit (205) receiving instructions from a processor (231), and breaking down each received instruction into a plurality of elementary operations to generate an elementary operation request flow; a circuit (203) of direct data transfer from or to said memory circuit (201), the transfer circuit (203) receiving instructions from the processor (231), breaking down each received instruction into a plurality of elementary operations to be performed in said memory circuit to generate an elementary operation request flow; an internal data exchange link (204) directly coupling said memory circuit (201) to the direct transfer circuit (203); and an arbitration circuit (309).

Abstract: The present description concerns a memory device (200) comprising: a memory circuit (201) implementing operations and performing elementary operations including a reading, a writing, or a computing operation; a control circuit (205) receiving instructions from a processor (231), and breaking down each received instruction into a plurality of elementary operations to generate an elementary operation request flow; a circuit (203) of direct data transfer from or to said memory circuit (201), the transfer circuit (203) receiving instructions from the processor (231), breaking down each received instruction into a plurality of elementary operations to be performed in said memory circuit to generate an elementary operation request flow; an internal data exchange link (204) directly coupling said memory circuit (201) to the direct transfer circuit (203); and an arbitration circuit (309).

Abstract: A method of 3D circuit conception comprising: providing, to a circuit conception tool, circuit design files representing a 3D circuit design including one or more first circuit elements attributed to a first tier of the 3D circuit and one or more second circuit elements attributed to a second tier of the 3D circuit; modifying, by the circuit conception tool, a property of the one or more first and/or second circuit elements to permit any of the second circuit elements to superpose, or be superposed by, any of the first circuit elements; and performing, by the circuit conception tool, placement and routing of the 3D circuit design based on a 2D circuit representation, interconnection nodes of the one or more second circuit elements being defined in one or more interconnection levels of the 2D circuit representation.

Abstract: A tier of a 3D circuit comprising: one or more macro circuits, each macro circuit comprising a plurality of macro cells arranged in an array, the macro cells being separated from each other by spaces; and interconnection vias positioned in the spaces between the macro cells.

Abstract: A method of 3D circuit conception comprising: providing, to a circuit conception tool, circuit design files representing a 3D circuit design including one or more first circuit elements attributed to a first tier of the 3D circuit and one or more second circuit elements attributed to a second tier of the 3D circuit; modifying, by the circuit conception tool, a property of the one or more first and/or second circuit elements to permit any of the second circuit elements to superpose, or be superposed by, any of the first circuit elements; and performing, by the circuit conception tool, placement and routing of the 3D circuit design based on a 2D circuit representation, interconnection nodes of the one or more second circuit elements being defined in one or more interconnection levels of the 2D circuit representation.

Abstract: A tier of a 3D circuit comprising: one or more macro circuits, each macro circuit comprising a plurality of macro cells arranged in an array, the macro cells being separated from each other by spaces; and interconnection vias positioned in the spaces between the macro cells.

Abstract: A two-phase asynchronous transmission circuit for transmitting data over a wired interface according to a two-phase asynchronous protocol, the transmission circuit including: N data output lines, where N is an integer equal to 3 or more, wherein the transmission circuit is capable of transmitting N unique data symbols, each of the output lines being associated with a corresponding one of the N data symbols, and the transmission circuit is adapted to transmit each data symbol by applying a voltage transition to the corresponding output line independently of the voltage state of the other output lines.

Abstract: An asynchronous integrated circuit is designed from a library of cells comprising at least one cell having parameters of signal propagation between a first terminal and a second terminal and between the second terminal and a third terminal depending on the parameter of signal propagation between the first and the third terminal. A synchronous integrated circuit corresponding to the asynchronous integrated circuit is synthesized using said cell to represent a portion of the asynchronous circuit, said cell being rated by a dummy clock signal. The synthesized integrated circuit is verified using the parameter of signal propagation between the first terminal and the third terminal to simulate the operation of said portion of the asynchronous circuit.

Abstract: A two-phase asynchronous transmission circuit for transmitting data over a wired interface according to a two-phase asynchronous protocol, the transmission circuit including: N data output lines, where N is an integer equal to 3 or more, wherein the transmission circuit is capable of transmitting N unique data symbols, each of the output lines being associated with a corresponding one of the N data symbols, and the transmission circuit is adapted to transmit each data symbol by applying a voltage transition to the corresponding output line independently of the voltage state of the other output lines.

Abstract: The invention relates to a rocket engine with an extendable divergent which includes an exhaust nozzle for the gases coming from a combustion chamber, the nozzle having a longitudinal axis (ZZ?) including a first portion defining a nozzle throat and a first fixed divergent section (12), at least one second extendable divergent section (16) with a larger cross-section than the first fixed divergent section (12) and a mechanism (18) for extending the second extendable divergent section (16) arranged outside the first and second divergent sections (12, 16). A rigid thermal protection screen (102) is positioned between the extending mechanism (18) and the first fixed divergent section (12). The thermal protection screen (102) has a convex wall (104) on the surface thereof that faces the first fixed divergent section (12).

Abstract: A method for automatic detection of defects in TSV vias formed in a layer of semiconductor material, this detection taking place before stacking this layer with a plurality of other layers of semiconductor material for the design of a multilayer chip integrated circuit, comprising: measurement on each of said TSV vias of at least one parameter derived from an electrical characteristic of the TSV vias; detection of defects in said TSV vias according to a comparison of the parameters measured with at least one reference parameter, and calculation of said at least one reference parameter using the measured parameters. The parameter measured on each of the TSV vias comprises an oscillation frequency value derived from a capacitive characteristic of the TSV vias.

Abstract: A device for powering an electronic circuit that applies at least a first voltage or a second voltage, different from the first voltage, to the electronic circuit. The device includes a performance monitor that receives an item of information defining a constraint and determines a first duration and a second duration, such that the operation of the electronic circuit at a first frequency associated with the first voltage for the first duration, and at a second frequency associated with the second voltage for the second duration, complies with the constraint. The device applies the first voltage and the first frequency to the circuit for the first duration and the second voltage and the second frequency for the second duration.

Abstract: An electronic circuit power supply device configured to selectively apply at least one first voltage or one second voltage to a power supply terminal of the electronic circuit that includes elements for applying to the power supply terminal a voltage variable from a value equal to the first voltage to a value equal to the second voltage and elements designed for selecting application of the second voltage to the power supply terminal when the variable voltage reaches the second voltage.

Abstract: This invention relates to the domain of Networks on Chips (NoC) and relates to a method of transferring data in a network on chip, particularly using an asynchronous “send/accept” type protocol. The invention also relates to a network on chip used to implement this method.

Abstract: A network and a data transmission method between elements in such a network using an asynchronous communication protocol of the “send/accept” type. At least one node in the network operations without an internal clock, this node determining a transfer hierarchy between two data packets to be routed to the same output, at least as a function of a priority channel information associated with each data packet.

Abstract: A device for powering an electronic circuit that applies at least a first voltage or a second voltage, different from the first voltage, to the electronic circuit. The device includes a performance monitor that receives an item of information defining a constraint and determines a first duration and a second duration, such that the operation of the electronic circuit at a first frequency associated with the first voltage for the first duration, and at a second frequency associated with the second voltage for the second duration, complies with the constraint. The device applies the first voltage and the first frequency to the circuit for the first duration and the second voltage and the second frequency for the second duration.

Abstract: An electronic circuit power supply device configured to selectively apply at least one first voltage or one second voltage to a power supply terminal of the electronic circuit that includes elements for applying to the power supply terminal a voltage variable from a value equal to the first voltage to a value equal to the second voltage and elements designed for selecting application of the second voltage to the power supply terminal when the variable voltage reaches the second voltage.

Abstract: This invention relates to the domain of Networks on Chips (NoC) and relates to a method of transferring data in a network on chip, particularly using an asynchronous “send/accept” type protocol. The invention also relates to a network on chip used to implement this method.

Abstract: The invention relates to the domain of networks on chip (NoC) and concerns a network and a data transmission method between elements in such a network using an asynchronous communication protocol of the “send/accept” type. At least one node in the network operates without an internal clock, this node determining a transfer hierarchy between two data packets to be routed to the same output, at least as a function of a priority channel information associated with each data packet.