Abstract: A multi-bit continuous-time sigma-delta analog-to-digital converter (ADC) has a differential input stage which receives an analog input signal current. A multi-bit feedback current digital-to-analog converter (IDAC) generates a multi-level feedback current depending on a digital feedback signal from a flash ADC. An integrator has a differential input that integrates the difference of the generated current by the multi-bit IDAC and the input signal current on a continuous-time basis. The input stage further comprises a first biasing current source and a second biasing current source which bias the input stage in a mid-scale condition. A first summing node connects to the first differential input line, a first differential input of the integrator and the first output branch. A second summing node connects to the second differential input line, a second differential input of the integrator and the second output branch.

Abstract: A sigma-delta digital-to-analog converter comprises a current digital-to-analog converter (IDAC) stage which generates a current depending on an input digital signal. An output current-to-voltage converter converts the generated signal to a voltage on a continuous-time basis. The amplifier used in the output current-to-voltage converter is chopper-stabilized. The converter can be single bit or multi-bit. The IDAC stage can be implemented with a pair of branches, a first branch comprising a first biasing current source and a second branch comprising a second biasing current source. The biasing current sources can be chopper-stabilized by connecting the bias current sources to the output current-to-voltage converter by a set of switches. The switches connect the biasing current sources to the output current-to-voltage converter in a first configuration and a second, reversed, configuration. This modulates flicker noise contributed by the bias current sources to the chopping frequency.

Abstract: An apparatus and a method for providing ESD protection in integrated circuits is provided. The apparatus includes ESD protection circuits between interface pins and a substrate of the integrated circuit to discharge ESD current at one interface pin of the integrated circuit through the substrate to an ESD reference point at another interface pin. The ESD protection circuits include reverse breakdown devices that become conductive when a reverse breakdown threshold level is exceeded. The method includes discharging electrostatic charge from a first interface pin of the integrated circuit to a second interface pin through a substrate of the integrated circuit.

Abstract: A digitally programmable infinite impulse response (IIR) filter particularly useful as a temporal averager. The filter comprises a voltage mode multiplying digital/analog converter (12) and two sample-and-hold circuits (10, 16). The first sample-and-hold circuit receives the input signal to the system and supplies its output signal to the reference voltage input terminal of the DAC. The second sample and hold circuit has its input terminal connected to the voltage output terminal of the DAC and has its output connected to the analog ground terminal of the DAC. A digital input code (D) supplied to the DAC controls its gain and the degree of noise rejection provided by the filter, by altering the frequency response of the filter.

Abstract: A CMOS D/A converter for use in a voltage-mode and having complementary-driven switch pairs for V.sub.ref and A.sub.gnd respectively. The "ON" gate voltage of the A.sub.gnd switch is adjusted in accordance with the value of V.sub.ref, to give switch V.sub.GS equality and therefore "ON" resistance matching with the V.sub.ref switch over a wide range of reference voltage. Circuits are shown for developing the A.sub.gnd gate voltage varying with V.sub.ref.