Abstract: A processor capable of performing a two-dimensional transform on high speed serial sampled analog raster scanned data and outputing the results in a parallel fashion so as to provide for a data rate reduction. The processor utilizes a charge coupled device (CCD), a matrix multiplier to perform a one-dimensional transform on data samples from a serial to parallel converter. The data is switched into a set of matrix multipliers which perform another transformation whose results are summed in an accumulator to yield the desired two-dimensional transformed coefficients.

Abstract: A processor capable of performing a two-dimensional inverse transform on high speed analog data and outputing the results in a display compatible format. The processor utilizes two charge coupled devices (CCD's), two matrix multipliers, which each perform a one-dimensional transform. The one-dimensional transformed data is multiplexed into a series to parallel converter so that another matrix multiplier can complete the two-dimensional transformation of the analog data.