Patents by Inventor Pasquale Cocchini

Pasquale Cocchini has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11797309
    Abstract: An apparatus and method for tracking speculative execution flow and detecting potential vulnerabilities.
    Type: Grant
    Filed: December 27, 2019
    Date of Patent: October 24, 2023
    Assignee: Intel Corporation
    Inventors: Carlos Rozas, Francis McKeen, Pasquale Cocchini, Meltem Ozsoy, Matthew Fernandez
  • Publication number: 20220300795
    Abstract: Systems, apparatuses and methods may provide for technology that includes a performance-enhanced decompression pipeline having first decoder hardware to convert variable length weights to fixed length keys, wherein the variable length weights are non-uniform quantization values, and second decoder hardware to convert the fixed length keys to bit value. In one example, the first length keys are compressed representations of the variable length weights and the bit values are bit accurate representations of the fixed length keys.
    Type: Application
    Filed: June 9, 2022
    Publication date: September 22, 2022
    Inventors: Yash Akhauri, Nilesh Jain, Pasquale Cocchini, Eriko Nurvitadhi
  • Publication number: 20210200551
    Abstract: An apparatus and method for tracking speculative execution flow and detecting potential vulnerabilities.
    Type: Application
    Filed: December 27, 2019
    Publication date: July 1, 2021
    Applicant: Intel Corporation
    Inventors: CARLOS ROZAS, FRANCIS MCKEEN, PASQUALE COCCHINI, MELTEM OZSOY, MATTHEW FERNANDEZ
  • Patent number: 6910196
    Abstract: A method and apparatus to obtain minimum cycle latency and maximum required time at a driver for an assignment of clocked and non-clocked repeaters in a topology comprising, determining whether a node in the topology is a leaf, and assigning covers if the node is a leaf. Determining whether the node in the topology comprises one branch or two branches. Assigning covers to each node and eliminating inferior covers. Merging covers, and deleting inferior covers taking into account a difference in interconnect latency associated with the covers. The above method may be modified with a heuristic to insert repeaters in a topology for a given latency at each driver-receiver pair.
    Type: Grant
    Filed: May 8, 2003
    Date of Patent: June 21, 2005
    Assignee: Intel Corporation
    Inventor: Pasquale Cocchini
  • Publication number: 20040225981
    Abstract: A method and apparatus to obtain minimum cycle latency and maximum required time at a driver for an assignment of clocked and non-clocked repeaters in a topology comprising, determining whether a node in the topology is a leaf, and assigning covers if the node is a leaf. Determining whether the node in the topology comprises one branch or two branches. Assigning covers to each node and eliminating inferior covers. (NOTE TO CLIVE: I removed the swap thing since the swap can be thought of as part of the merge operation . . . ). Merging covers, and deleting inferior covers taking into account a difference in interconnect latency associated with the covers. The above method may be modified with a heuristic to insert repeaters in a topology for a given latency at each driver-receiver pair.
    Type: Application
    Filed: May 8, 2003
    Publication date: November 11, 2004
    Inventor: Pasquale Cocchini