Patents by Inventor Pasquale Conenna
Pasquale Conenna has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230017305Abstract: A variety of applications can include apparatus or methods that provide a well ring for resistive ground power domain segregation. The well ring can be implemented as a n-well in a p-type substrate. Resistive separation between ground domains can be generated by biasing a n-well ring to an external supply voltage. This approach can provide a procedure, from a process standpoint, that provides relatively high flexibility to design for chip floor planning and simulation, while providing sufficient noise rejection between independent ground power domains when correctly sized. Significant noise rejection between ground power domains can be attained.Type: ApplicationFiled: April 27, 2022Publication date: January 19, 2023Inventors: Mattia Cichocki, Vladimir Mikhalev, Phani Bharadwaj Vanguri, James Eric Davis, Kenneth William Marr, Chiara Cerafogli, Michael James Irwin, Domenico Tuzi, Umberto Siciliani, Alessandro Alilla, Andrea Giovanni Xotta, Chung-Ping Wu, Luigi Marchese, Pasquale Conenna, Joonwoo Nam, Ishani Bhatt, Fulvio Rori, Andrea D'Alessandro, Michele Piccardi, Aleksey Prozapas, Luigi Pilolli, Violante Moschiano
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Patent number: 10049038Abstract: A bus controller has a displacer, an arithmetic logic unit coupled to the displacer, and a replacer selectively coupled to the displacer and the arithmetic logic unit.Type: GrantFiled: July 27, 2015Date of Patent: August 14, 2018Assignee: Micron Technology, Inc.Inventors: Luca De Santis, Pasquale Conenna
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Publication number: 20150331792Abstract: A bus controller has a displacer, an arithmetic logic unit coupled to the displacer, and a replacer selectively coupled to the displacer and the arithmetic logic unit.Type: ApplicationFiled: July 27, 2015Publication date: November 19, 2015Applicant: MICRON TECHNOLOGY, INC.Inventors: Luca De Santis, Pasquale Conenna
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Patent number: 9128894Abstract: A bus controller has a displacer, an arithmetic logic unit coupled to the displacer, and a replacer selectively coupled to the displacer and the arithmetic logic unit.Type: GrantFiled: February 3, 2014Date of Patent: September 8, 2015Assignee: Micron Technology, Inc.Inventors: Luca De Santis, Pasquale Conenna
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Publication number: 20140156904Abstract: A bus controller has a displacer, an arithmetic logic unit coupled to the displacer, and a replacer selectively coupled to the displacer and the arithmetic logic unit.Type: ApplicationFiled: February 3, 2014Publication date: June 5, 2014Applicant: MICRON TECHNOLOGY, INC.Inventors: Luca De Santis, Pasquale Conenna
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Patent number: 8667232Abstract: A controller for a memory device and methods are provided. The controller has an updateable register bank adapted to send a first signal to an analog/memory core of the memory device for controlling operation of the analog/memory core. The analog/memory core has an array of flash memory cells and supporting analog access circuitry. A bus controller is coupled to the register bank. The bus controller is adapted to receive a second signal from the register bank and to send a third signal to the register bank for updating the register bank. A select register is coupled to the register bank. A processor is coupled to the bus controller and the select register.Type: GrantFiled: January 4, 2010Date of Patent: March 4, 2014Assignee: Micron Technology, Inc.Inventors: Luca De Santis, Pasquale Conenna
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Publication number: 20100174855Abstract: A controller for a memory device and methods are provided. The controller has an updateable register bank adapted to send a first signal to an analog/memory core of the memory device for controlling operation of the analog/memory core. The analog/memory core has an array of flash memory cells and supporting analog access circuitry. A bus controller is coupled to the register bank. The bus controller is adapted to receive a second signal from the register bank and to send a third signal to the register bank for updating the register bank. A select register is coupled to the register bank. A processor is coupled to the bus controller and the select register.Type: ApplicationFiled: January 4, 2010Publication date: July 8, 2010Inventors: Luca De Santis, Pasquale Conenna
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Publication number: 20100027340Abstract: Pattern dependent string resistance compensation of a memory device is generally described. In one example, an electronic device includes a first string of memory cells and a first bit line coupled with the first string of memory cells wherein a memory cell of the first string of memory cells is read, in part, by pre-charging the first bit line through the first string of memory cells to compensate for resistance of unselected cells in the first string of memory cells.Type: ApplicationFiled: July 31, 2008Publication date: February 4, 2010Inventors: Ercole Rosario Di Iorio, Pasquale Conenna
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Patent number: 7644240Abstract: A controller for a memory device and methods are provided. The controller has an updateable register bank adapted to send a first signal to an analog/memory core of the memory device for controlling operation of the analog/memory core. The analog/memory core has an array of flash memory cells and supporting analog access circuitry. A bus controller is coupled to the register bank. The bus controller is adapted to receive a second signal from the register bank and to send a third signal to the register bank for updating the register bank. A select register is coupled to the register bank. A processor is coupled to the bus controller and the select register.Type: GrantFiled: July 20, 2006Date of Patent: January 5, 2010Assignee: Micron Technology, Inc.Inventors: Luca De Santis, Pasquale Conenna
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Patent number: 7587560Abstract: A controller for a memory device and methods are provided. The controller has an updateable register bank adapted to send a first signal to an analog/memory core of the memory device for controlling operation of the analog/memory core. The analog/memory core has an array of flash memory cells and supporting analog access circuitry. A bus controller is coupled to the register bank. The bus controller is adapted to receive a second signal from the register bank and to send a third signal to the register bank for updating the register bank. A select register is coupled to the register bank. A processor is coupled to the bus controller and the select register.Type: GrantFiled: July 20, 2006Date of Patent: September 8, 2009Assignee: Micron Technology, Inc.Inventors: Luca De Santis, Pasquale Conenna
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Patent number: 7318181Abstract: A circuit to monitor the activity of a memory device during program/erase operations that are managed by a ROM-based microcontroller. Different signals can be monitored according to different test modes. The ROM-based microcontroller is triggered by a clock that can be connected to an internal fixed frequency oscillator or to an external clock source for which the frequency can be varied from 0 Hz to any frequency required by the application. The circuit outputs state machine status data, read only memory addresses, and memory status information in a series of multiplexing operations to provide a tester with the ability to determine the state of a memory device during various memory operations.Type: GrantFiled: June 24, 2005Date of Patent: January 8, 2008Assignee: Micron Technology, Inc.Inventors: Giovanni Naso, Pasquale Pistilli, Luca De Santis, Pasquale Conenna
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Patent number: 7272683Abstract: A controller for a memory device and methods are provided. The controller has an updateable register bank adapted to send a first signal to an analog/memory core of the memory device for controlling operation of the analog/memory core. The analog/memory core has an array of flash memory cells and supporting analog access circuitry. A bus controller is coupled to the register bank. The bus controller is adapted to receive a second signal from the register bank and to send a third signal to the register bank for updating the register bank. A select register is coupled to the register bank. A processor is coupled to the bus controller and the select register.Type: GrantFiled: November 25, 2003Date of Patent: September 18, 2007Assignee: Micron Technology, Inc.Inventors: Luca De Santis, Pasquale Conenna
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Publication number: 20060259713Abstract: A controller for a memory device and methods are provided. The controller has an updateable register bank adapted to send a first signal to an analog/memory core of the memory device for controlling operation of the analog/memory core. The analog/memory core has an array of flash memory cells and supporting analog access circuitry. A bus controller is coupled to the register bank. The bus controller is adapted to receive a second signal from the register bank and to send a third signal to the register bank for updating the register bank. A select register is coupled to the register bank. A processor is coupled to the bus controller and the select register.Type: ApplicationFiled: July 20, 2006Publication date: November 16, 2006Inventors: Luca De Santis, Pasquale Conenna
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Publication number: 20060259714Abstract: A controller for a memory device and methods are provided. The controller has an updateable register bank adapted to send a first signal to an analog/memory core of the memory device for controlling operation of the analog/memory core. The analog/memory core has an array of flash memory cells and supporting analog access circuitry. A bus controller is coupled to the register bank. The bus controller is adapted to receive a second signal from the register bank and to send a third signal to the register bank for updating the register bank. A select register is coupled to the register bank. A processor is coupled to the bus controller and the select register.Type: ApplicationFiled: July 20, 2006Publication date: November 16, 2006Inventors: Luca De Santis, Pasquale Conenna
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Patent number: 6977852Abstract: A circuit to monitor the activity of a memory device during program/erase operations that are managed by a ROM-based microcontroller. Different signals can be monitored according to different test modes. The ROM-based microcontroller is triggered by a clock that can be connected to an internal fixed frequency oscillator or to an external clock source for which the frequency can be varied from 0 Hz to any frequency required by the application. The circuit outputs state machine status data, read only memory addresses, and memory status information in a series of multiplexing operations to provide a tester with the ability to determine the state of a memory device during various memory operations.Type: GrantFiled: October 30, 2003Date of Patent: December 20, 2005Assignee: Micron Technology, Inc.Inventors: Giovanni Naso, Pasquale Pistilli, Luca De Santis, Pasquale Conenna
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Publication number: 20050240851Abstract: A circuit to monitor the activity of a memory device during program/erase operations that are managed by a ROM-based microcontroller. Different signals can be monitored according to different test modes. The ROM-based microcontroller is triggered by a clock that can be connected to an internal fixed frequency oscillator or to an external clock source for which the frequency can be varied from 0 Hz to any frequency required by the application. The circuit outputs state machine status data, read only memory addresses, and memory status information in a series of multiplexing operations to provide a tester with the ability to determine the state of a memory device during various memory operations.Type: ApplicationFiled: June 24, 2005Publication date: October 27, 2005Inventors: Giovanni Naso, Pasquale Pistilli, Luca De Santis, Pasquale Conenna
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Publication number: 20050015541Abstract: A controller for a memory device and methods are provided. The controller has an updateable register bank adapted to send a first signal to an analog/memory core of the memory device for controlling operation of the analog/memory core. The analog/memory core has an array of flash memory cells and supporting analog access circuitry. A bus controller is coupled to the register bank. The bus controller is adapted to receive a second signal from the register bank and to send a third signal to the register bank for updating the register bank. A select register is coupled to the register bank. A processor is coupled to the bus controller and the select register.Type: ApplicationFiled: November 25, 2003Publication date: January 20, 2005Inventors: Luca De Santis, Pasquale Conenna
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Publication number: 20040213060Abstract: A circuit to monitor the activity of a memory device during program/erase operations that are managed by a ROM-based microcontroller. Different signals can be monitored according to different test modes. The ROM-based microcontroller is triggered by a clock that can be connected to an internal fixed frequency oscillator or to an external clock source for which the frequency can be varied from 0 Hz to any frequency required by the application. The circuit outputs state machine status data, read only memory addresses, and memory status information in a series of multiplexing operations to provide a tester with the ability to determine the state of a memory device during various memory operations.Type: ApplicationFiled: October 30, 2003Publication date: October 28, 2004Applicant: Micron Technology, Inc.Inventors: Giovanni Naso, Pasquale Pistilli, Luca De Santis, Pasquale Conenna