Abstract: A command user interface with via mask programmability includes a decoder with transistors selectively coupleable to one of an input or its complement. This is accomplished in one way by making vias in an appropriate location to allow interconnection of the appropriate contact and the gate of the transistor.

Abstract: A command user interface with via mask programmability includes a decoder with transistors selectively coupleable to one of an input or its complement. This is accomplished in one way by making vias in an appropriate location to allow interconnection of the appropriate contact and the gate of the transistor.

Abstract: A command user interface with via mask programmability includes a decoder with transistors selectively coupleable to one of an input or its complement. This is accomplished in one way by making vias in an appropriate location to allow interconnection of the appropriate contact and the gate of the transistor.

Abstract: Methods and apparatus to facilitate erasure of multiple sectors of a memory device without the need for externally-supplied erase potentials are advantageous for device testing. During a scan of sector addresses, sector tagging blocks of a memory device provide an output signal to a write state machine indicating whether the addressed sector is tagged for erasure. The sector tagging blocks facilitate resetting of tags on a global basis and setting of tags on a single, bank-wide and/or global basis. Once initiated, the erase operation proceeds to erase each tagged sector of the memory device in sequence without the need for externally-supplied erase potentials and without the need for further direction of the tester hardware. The methods are particularly useful for erasing all sectors of a memory device or all sectors of one memory bank of the memory device.

Abstract: A system and method for a write state machine for non-volatile memory is disclosed. The write state machine has an associated read only memory for storing instructions for operation of the non-volatile memory.

Abstract: The various embodiments provide for programming floating-gate, or flash, memory devices by writing a block of data words to a volatile storage media from an external processor and programming the block of words to the nonvolatile flash memory cells from the volatile storage media without the need for further input from the external processor. In this manner, a block of words may be programmed into the flash memory device using a single write command and avoiding the need for a verify operation after programming each word. By utilizing an internal volatile storage media to receive the block of words prior to writing the individual words to the memory array, the external processor is free to perform other tasks while the programming and verification are performed autonomously by the memory device. Using an external power supply facilitates parallel transfer from the internal volatile storage media to the nonvolatile flash memory cells.

Abstract: A system and method for a write state machine for non-volatile memory is disclosed. The system includes an array of memory cells and a write state machine for controlling operations on the array of memory cells. The write state machine has an associated read only memory for storing instructions for operation of the non-volatile memory. The write state machine is adapted to suspend an execution of one of the operations during an action on a block in the non-volatile memory which is not being accessed by the write state machine.

Abstract: Methods and apparatus to facilitate erasure of multiple sectors of a memory device without the need for externally-supplied erase potentials are advantageous for device testing. During a scan of sector addresses, sector tagging blocks of a memory device provide an output signal to a write state machine indicating whether the addressed sector is tagged for erasure. The sector tagging blocks facilitate resetting of tags on a global basis and setting of tags on a single, bank-wide and/or global basis. Once initiated, the erase operation proceeds to erase each tagged sector of the memory device in sequence without the need for externally-supplied erase potentials and without the need for further direction of the tester hardware. The methods are particularly useful for erasing all sectors of a memory device or all sectors of one memory bank of the memory device.

Abstract: A multiple partition memory array has a command user interface for each partition, and a logic interface. The logic interface receives signals from each of the command user interfaces to restrict executable commands in the command user interfaces to those commands that will not tax the system given the current status of each of the command user interfaces.

Abstract: A command user interface with via mask programmability includes a decoder with transistors selectively coupleable to one of an input or its complement. This is accomplished in one way by making vias in an appropriate location to allow interconnection of the appropriate contact and the gate of the transistor.

Abstract: A system and method for a write state machine for non-volatile memory is disclosed. The write state machine has an associated read only memory for storing instructions for operation of the non-volatile memory.

Abstract: System for enabling the use of semiconductor dynamic memories having faulty locations therein where the memory is organized in banks for forming an elementary information word. The system identifies all homologous address locations which are not faulty, and the non-faulty locations are then stored as a map in a non-volatile read-only-memory related to the memory bank so as to form a transcoding table. Access to the memory blocks involves the use of a central processing unit requesting access to a block identified by a sequential address. The system then provides for associating the material address of a block of the memory array to the logical address, this association or transcoding operation being carried out by the non-volatile read-only-memory.